High Speed Interface Forum - Recent Threads

May DS90UB913 can support 1920x1080p 30 frames?

Chen Bogey — Thu, 16 May 2013 11:43:14 GMT

Dear Sir

Good days,

May we check with you if DS90UB913 can support 1920x1080p 30 frames?

As we know DS90UB913 support 10~100M pixel colock .

from as below formula ==>Pixel Clock = H-pixels x V-pixels x Fps* x (1 + Percent Blanking**)

Here i let (1 + Percent Blanking**) = 1.4

and calculate 1920x1080x30 x1.4 around 87M pixel clock, i think DS90UB913 should be ok, but may you pls help double check?

Best Regards,

Bogey

LMH0387 Launch amplitude Fine Control Resister(02h, 6:3)

TKOB — Mon, 20 May 2013 10:15:08 GMT

I'd like to confirm the description of Launch amplitude fine Control resisters(02h, 6:3). On the LMH0387 datasheet(REVICED April 2013); Almost all settings of gain are +20% higher than LM0384's settings. Are there correct ? (Did you set the base gain of LMH0387 higher ?)

About LMH1982

gang shao — Tue, 21 Aug 2012 02:13:47 GMT

LMH1982 Application

If the input format is 625i and the output format 1080i/50 ,then how to program the register and what is the programming sequence?

IBIS Model for the SN65MLVD047A

David Hildebrand — Wed, 15 May 2013 21:10:52 GMT

Do we have an IBIS model available for the SN65MLVD047A?

Thanks, David

---------------------------------
David Hildebrand
Analog Field Applications
South Region
Texas Instruments, Inc.
Office: 214-479-0917
Cell: 972-841-6499
david.hildebrand@ti.com

---------------------------------

DS90CR286A deserial problem

cylinc — Wed, 08 May 2013 03:27:31 GMT

Hi, I have a board with TW8816 as LCD controller and DS90CR285 as transmitter, it's for an old car LCD display and works fine whatever the input of TW8816 is RGB888 or CVBS.

Recently, i made a deserializer board using DS90CR286A,and these two board were connected using board-to-board connector. When the input to TW8816 is RGB888,the singal deserialed good,but when the input is CVBS,then the deserialed signal is very bad. In both case, I measured the FPCLK singal at pin RXOUT1 which was deserialed from RXIN0+/- pair.The frequency of FPCLK in both cases were almost the same about 11MHz.

And the RXCLKOUT was good in both case. Because the original board can light the car LCD dislay all right, i have no reason to be suspicious about it. I can't fingure out why there is such difference in these two cases? Any advice or how should i to find out where may problem be?

Blow is the screeshot of the FPCLK wave and the LVDS signal PCB layout.

Problem with the SERDESUR-65USB DemoBoard from TI

Thomas Feller — Fri, 26 Apr 2013 06:52:13 GMT

Hi,

I have a Controller Board with the T20 (Cortex A9, Windows EC 7) connected to an 5,7" VGA Display with the parallel Inteface ==> this works fine.

Then I have connected the two SERDESUR-65USB Boards between the Controller Board and the Display. The LCD displays with some flickering pixels.

The PASS and the LOCK output of the DS90UR906 shows errors. I tried with the De-Emphasis Option, but without success.

The VDDI voltage is 3.3V.

Any idea ?

Thanks & best regards

Thomas

FPD Link III - DS90UB914 wake up in the wrong mode

Matthias Zeilinger — Wed, 15 May 2013 08:52:23 GMT

Hi,

we are developing a camera with the chip set DS90UB913 and DS90UB914. The pixel clock from the image sensor is 12 MHz, so we want to use the 12 bit low frequency mode of the devices. There is a mode pin at the DS90UB914 which is put to GND in our design. This should indicate the right mode to the device at power up as mentioned in the datasheet.

But after power up, if we read the mode register (read only), the device is in 10 bit high speed mode.

The second issue is the clock output of the deserializer DS90UB914. We transmit the video data with 12 MHz from the sensor, but the deserializer has only 6 MHz clock output. The device devides the clock internally which we can't accept.

I would be glad if anyone could help me.

Best regards,

Matthias

DP83848C phy autonegotiation and link issues

Benjamin Babjak — Thu, 21 Jun 2012 17:13:44 GMT

Hi,

We are trying to build a sensor platform using the DP83848C physical layer ethernet interface. We took the SmartFusion Evaluation Kit from Microsemi (http://www.actel.com/products/hardware/devkits_boards/smartfusion_eval.aspx) as our reference design, and built our board basically copying the relevant parts from their schematic, the only difference being the RJ-45 connector. We've found that our boards fail at the autonegotiation step, no link is established.

Here is what we have tried so far:

1. We've made sure that supply voltage and 50 MHz clock are present, device is not powered down (pin 7), and is not reseting (pin 29).

2. With autonegotiation and Auto-MDIX turned on we've measured the signals on both the TD and RD pins, and verified that normal link pulses (NLP as defined in the autonegotiation specification) are present. We've found however that the signals look unlike the ones seen in Application Note 1519 DP83848.

3. If connected to an ethernet hub our device was not able to successfully autonegotiate, even though the ethernet hub was sending fast link pulse bursts with the acknowledge bit on, meaning that it had correctly received the link code word from our device.

4. We've assumed that the inability of our device detecting link code words from the hub, and the difference in pulse shapes are due to the different RJ-45 connector (J0G-0007NL as opposed to . Unfortunately they were not pin compatible, so we've used a 2 inch long ribbon cable to connect to the PCB.

The pulse shapes were still different, our device was still unable to detect link code words. In the picture the longer signals are the differential signals measured on the working evaluation kit, the shorter signals with the higher amplitudes are the differential signals we have measured on our board.

5. We've checked our software as well, we start out with a reset (bit 15 in BMCR), then we wait more than 3 us and enable autonegotiation (bit 12), restart autonegotiation (bit 9), and enable collision test (bit 7) with one write to BMCR.

Any ideas what else we could/should check?

Our design is open-source ( http://code.google.com/p/marmote/source/browse/#svn%2Ftrunk ) the schematics of the board can be found here: http://code.google.com/p/marmote/source/browse/trunk/hardware/MainBoard_RevA/MainBoard_RevA_Sch.pdf (click "View raw file" to download pdf).

Thanks,

Benjamin

Replaceament of MAX3872 and ADN2855 in GPON application

Ted Xu — Tue, 14 May 2013 09:58:06 GMT

Hi team

My customer kicked off a GPON projects,where MAX3872 and ADN2855 are suitable, Do we have related replcement solution ?

Thanks

DS100MB203　Questions about 3.3V mode / SlaveMode

Tomohiko Sugiyama — Thu, 16 May 2013 12:39:24 GMT

Please let me confirm some questions about DS100MB203.

(1) Is it possible to switch in SEL1 pin SlaveMode setting?

In order to set the SlaveMode, READEN/SEL1 should be hold to Low.

Is "READEN" Low during startup ?

(2)Regarding to the Datasheet of DS100MB203 on page P12, Table 1. 4?Level Control Pin Settings "Voltage at Pin" is "0.98 x VDD".

Is this description correct?

*I think that this voltage should be "0.98 x VIN" in 3.3V mode.

Best regards

SERDESUB-21USB I2C communication in Display mode

Lee Anthony — Thu, 18 Apr 2013 12:39:28 GMT

Hi,

I am currently evaluating the SERDESUB-21USB kit and I am experiencing problems with the I2C interface when operating the SERDES chip set in the Display mode, and I was hoping somebody could point me in the right direction as to what might be causing me the problem.

The SERDESUB-21USB link is working reliably (Lock signal stable, witnessed by setting a trigger for falling edge) and I am providing a 20 MHz signal on the Ser (PCLK pin), for which I am recovering reliably at the Des end (PCLK pin). Also the GPIO pin(s) functionality is working correctly; therefore I am confident that the SERDES link is working reliably.

A Diagram of my I2C set-up is shown as follows:-

With reference to the SERDESUB-21USB (P21) User’s Guide the Dill switches for configuring Master / Slave relationship (M_S pin) have been set as follows:-

DS90UB903Q = H (Slave)
DS90UB904Q = L (Master)

I2C bus speed at the Master is configured as 100 kHz

Also in line with configuring the set-up the following register values have been set:-

SER 0x06 = 0xC0 (Default anyway at power-up)

SER 0x07 = 0x9A

DES 0x08 - 0x17 = 0x00 (Default)

The problem I am experiencing is when trying to send a command to the AR1021 (Touch screen controller), which have been verified as working correctly when not passing the I2C over the SerDes link.

An example command (Bytes seen) has been provided within the attached file (Image insertion proivded poor quality) see screen shot of the logic analyser image highlighting the issue I am seeing. Logic Analyser connections are made at I2C_SER at the O/P of the Microchip Serial Analyser and I2C_DES at the O/P of the DS90UB904Q Deserialiser.

Disable Touch

Send: - 0x9A, 0x00, 0x55, 0x01, 0x13 This is sent O.K and timing seems O.K (Approx 1us delay between SER and DES clock pulses)

Receive: - 0x9B, 0x55, 0x02, 0x00, 0x13 Clock pulses are seen on the Des line, when 0x55 is sent by the AR1021 however these are not being re-produced on the Ser I2C bus and timing appears to become sparadic ?

From looking at the datasheet and also from correspondance from Microchip both the Master (Serial Analyser) and Slave (AR1021) both support clock stretching....

Any ideas on resolving this issue would be appreciated as I am keen to implement this chip set in my future design.

Thanks Lee Smith

DS80PCI800 - LInk Bringup Strategy

John Marcolina — Tue, 02 Apr 2013 22:31:29 GMT

We are planning to have 2 repeaters on a Gen3 PCIe link. We need 2 repeaters due to the length of the channel. Are there any recommendations or guidelines on how to set the repeater EQ/de-emphasis parameters when we bring up the link?

DS80PCI800 Lane Inversions OK?

John Marcolina — Wed, 15 May 2013 19:23:32 GMT

Hello,

We'd like to swap P/N on some lanes of this device to improve PCB routing. We would only swap input and output together, so that the endpoints would not see an inversion. I was wondering if there are any problems with doing this, with regards to receive detection, initialization, or anything else.

Thanks in advance.

RE: duplicate DVI SIGNAL

Steve Clynes — Wed, 15 May 2013 14:36:09 GMT

Do you need to support HDCP copy protection too?

If you need HDCP copy protection then the answer is no since this requires the video stream to be completely decoded and dual re-encoded. This is an extension of an application called a 'repeater'.

If you do not require HDCP then it is sufficient to simply buffer all the signals.

This question is probably better posted to the interface forums since this is not a video decoder/converter problem. I will try to transfer the question for you.

BR,

Steve

Balun for DS90UB925Q and DS90UB926Q

R. Scalick — Tue, 14 May 2013 16:23:04 GMT

Hallo,

could you give me a recommendation for a Balun for DS90UB925Q and DS90UB926Q ? What are the requirements for this Balun. (Datarate max. 1,485GBit/s)

I tried to find at Toko and Murata. My reqirements are impedance transormation from 100Ohm (balanced) to 50Ohm unbalanced and back. I think that this could be the same componet.

regards

Rudi

TLK1501 TTL Input Structure

Jeffrey McCasland — Mon, 13 May 2013 23:54:14 GMT

Could you please tell me if there are any protection diodes on the TTL inputs of the TLK1501? I'm curious to know if two of these devices may have its TTL inputs connected in parallel with series resistors allowing for a cold spare application. i.e. one device powered OFF with the other ON. If so, do you have an application note or reference design indicating this?

Thanks!

Jeffrey

DS64MB201 - Tj(MAX)

Kawai — Tue, 23 Apr 2013 06:09:06 GMT

Hi, could you please let me confirm about the Junction Temperature description in the datasheet ?

In the datasheet P.5 Junction Temperature Range is said as "+105C" for TJ(MAX).

Isn't this a typo ?

I think 125C would be correct.

Family product of DS64BR401 and DS100MB203 have TJ(MAX) = 125C in the ABS MAX Ratings.

Best Regards,

Kawai

FPD-Link III Tester

Robert Margit — Tue, 14 May 2013 19:27:01 GMT

Dear Everybody!

First of all I would like to thank you for your answers. I am new on this forum.

We would like to make a test for a device that has FDP-Link III input and FDP-Link Output.

Two different picture ( RGB 010101 …. and 1010101….) would be sent to its input.

We should receive these picture on the output of the device and compare with the pictures that have sent to the input of the device. (compare the input picture with output picture)

I would have some questions.We have to convert the FDP-Link signal to RGB888.

What do you think about can we use DS90CF386MTD in order to convert the FPD-Link?

( http://www.ti.com/lit/ds/symlink/ds90cf386.pdf )?
I have attached the figure about the plan, could you check these values are correct?

Does somebody have any other type of instrument for this special function?

Generator-Serializer: DS90UB925Q ( http://www.ti.com/lit/ds/symlink/ds90ub925q-q1.pdf )

Deserializer: DS90UH928Q ( http://www.ti.com/lit/ds/symlink/ds90uh928q-q1.pdf )

I am looking forward for your answers.

Thank you so much.

Best Regards

Robert Margit

(Please visit the site to view this file)

DS90CR288 split to multiple DS90CR287

Jim Suriano — Tue, 14 May 2013 12:40:43 GMT

We have an application where we are using the DS90CR288 to deserialize CameraLink input data and split that to multiple DS90CR287 for retransmission. The DS90CR288 is functioning correctly and deseralizing the data properly, however the DS90CR287 is not generating proper LVDS outputs. From the data sheet it mentioned that the DS90CR287 shouldn't be enable until after the clock is available and we have delayed the turn on time of the chip appropriately but have still not gotten any output generated.

At this point we are not sure what else to try. We had another prototype board that functioned properly once we added the appropriate delay to turning on the DS90CR287 to account for the delay in the clock signal being generated (which we did through the use of a manual switch). We've since added a way to handle that automatically but that does not seem to have solved the issue.

Thanks,

Jim

Aleksander Belkin

Alexander Belkin — Thu, 11 Apr 2013 11:46:09 GMT

Hello,

I have a question of TLK10002 Line Alignment.

TLK10002 is connected with the link partner device (FPGA Spartan 6) by means of four lines.

Data flows in all lines are independent.

Line alignment is not required.

Question:

Whether TLK will carry out data transmission to the HS line if not to carry out alignment of LS lines?

Thank you,

Aleksander

DS90UB925Q and DS90UB926Q

R. Scalick — Mon, 13 May 2013 12:05:12 GMT

Hallo,

1.) I would like to ask if this serdes components can be used for a 20bit BT.1120 HD video transmission ? We have 1080p with 30 frames. (1,485GBit/s) and a cable length of 2m to 5m.

2.) I have seen that this components have only a STP interface; is it possible, to do the connection with only one single coax conecction and the other out/in-put terminated ? (-6dB in signal)

3.) Is it a problem if the sync signals are embedded in the "video-datas" ?

many thanks for your infos and kind regards

Rudi

SN65LVDS4

eli — Wed, 24 Apr 2013 12:00:09 GMT

Which is the recommended driver to be used with the SN65LVDSLVDS4, a DIFFERENTIAL LINE DRIVER?

Is it the SN65LVDS1?

LMH1982 - square pixel clock generation

John White1 — Sun, 12 May 2013 17:58:09 GMT

Is it possible to program the LMH1982 to generate a 29.5MHz clock when genlocked to a PAL video signal, and to generate a 24.546MHz clock when genlocked to a NTSC signal?

These clock signals allow me to generate a square pixel format for my graphics application.

DS25BR100 Speed

Andrey Lyubimcev — Mon, 13 May 2013 07:34:35 GMT

Is it possible to use DS25BR100 at speeds of 1.25 Gbit / s? Necessary to extend the SGMII interface on the 400mm.

DS100DF410 : better channel combination when customer use only two channels

Hiroshi Kezuka — Thu, 09 May 2013 06:57:40 GMT

Dear team,

Customer use only 2 channel of DS100DF410. Then customer asked us is there better channel combination to improve performance when customer use only 2 channel(ex. ch0 and ch3).

I think it is better to use ch0 and ch3, and power down ch1 and ch2.
Is my understand correct?

Regards,
Hiroshi Kezuka