The TLK2711A datasheet states that the device's receiver will only achieve byte alignment on the 0011111 comma. Is this intended to represent the first seven bits of the 10 bit line codes for K codes K28.1, K28.5, and K28.7, meaning that byte alignment will be achieved if any of those three K codes are used?
Yes 0011111 (comma) associated with K28.1, K28.5, and K28.7 K codes are used to achieve byte alignment provided that they are of the correct running disparity. The TLK2711A keys off of negative running disparity versions of the codes.
When the TLK2711 syncs to a comma code, assuming that we send the receiver a K28.5 followed by a D5.6 (as suggested in the TLK1501 datasheet) , does the 16-bit output data always have the K code on the MS byte and the D code in the LS byte? Or is it possible to have the K-code show up in the LS byte, and the D code in the MS byte of the next output word? In other words, is the 16-bit output data always synced to the full (20 bit) width of the idle sequence?
Also, are there any HDL (VHDL or Verilog) models available which demonstrate the transmit portion of the TLK2711? I'd like to be able to simulate the data patterns I need to generate to the receiver to make sure my transmitter is generating correct data patterns.
Once the byte alignment is achieved, the K-code and D-Code byte locations will remain consistent.
I have attached the model we have for the TLK2711. Please note the model is for Modelsim environment. This is the only model we currently have for the device.
Thanks for the model.
Regarding the byte alignment, I'm not worried about it shifting with respect to the byte period once a sync has been established, but rather what the ordering will be as a consequence of the sync being established. In other words, where in the 16-bit field will the K-code appear, and where in the 16-bit field will the data code appear?
I see two possibilities for the data ordering.
Possibility #1- sync appears within one 16 bit output word of the TLK2711A:
TLK2711 output bus -> [15 8] [7 0]
Word 0 data -> [ K28.5 ] [ D5.6 ]
Possibility #2 - sync appears across two 16-bit output words of the TLK2711A:
Word 0 data -> [ xxxxxx ] [ K28.5 ]
Word 1 data -> [ D5.6 ] [ xxxxx ]
If either ordering can happen, then I'll need to worry about making sure I can deal with subsequent data that is unaligned to the 16-bit output words of the TLK2711A. If, on the other hand, syncs are always presented as in possibility 1, then I can count on having aligned 16-bit output data from the TLK2711A.
The K-codes containing RD- commas are always mapped to the lower (LS) byte of the parallel output bus. This means that the second possibility you illustrated is the only one that should occur, and receiving additional K28.5 codes will not throw off the 16-bit word alignment.
I hope this helps. Let me know if you have any additional questions.
Best regards,Max RobertsonAnalog Applications EngineerTexas Instrumentsmemail@example.com
I was very happy to find the TLK2711 verilog model you posted on the forum, but as I'm implementing in a simulation, I noticed that device signals PRE, TKLSB, TKMSB (inputs) and RKMS and RKLSB (outptus) are not in the module. On the other hand, the verilog module contians inputs TX_EN, TX_ER and RREF, and outputs RX_DV and RX_ER that are not listed in the device. Can you ellaborate on any significance this has when using the model?
Thanks in advance
The model for the TLK2711A was developed from the parent device model (TLK2501) and therefore it looks like the TLK2711A model retained some of the pin naming conventions used in the TLK2501. For the sake of the TLK2711A model, please use the following reassignments:
PRE = RREF
TKLSB = TX_ER
TKMSB = TX_EN
RKMSB = RX_DV
RKLSB = RX_ER
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