Please advise me on how LMH1983 assert/de-assert NOLOCK signal.
Referring the datasheet, LMH1983 decide NOLOCK condition based on two registers,LOCK_STEP_SIZE (0x2D) & LOCK1_THRESHOLD (0x1C).LOCK_STEP_SIZE (0x2D) specifies amount of validation permitted on VC_LF pinLOCK1_THRESHOLD (0x1C) specifies the number of HIN pulse before the device Assert NOLOCK.
Q1. Please let me know the precise logic of asserting and de-asserting NOLCK. Does device refers only LOCK_STEP_SIZE when it de-assert NOLOCK or checks the number of HIN pulse hit in a window as well?
Q2. I suppose that LOCK1_THRESHOLD check the number of HIN pulse in a specified window. If so, how much the size of the window?
Q3. On page 28 of the LMH1983 data sheet, there is ate following description. Setting “1”, into the LOCK_STEP_SIZE may make the lock time long. What do you think?
To minimize the amount of time that it takes to assert lock,load the LOCK_STEP_SIZE register (register #45, 0x2D )with a value of 1, and the LOCK_THRESHOLD register (register#28, 0x1C) with a value of 31. The effect of this can beseen in the 'Faster Reaction Mode timing diagram shown below
When the CLOCK1 PLL is in a LOCK condition, the VCXO frequency (or a multiple of it) is exactly the same as the reference frequency. If the reference frequency has no jitter or wander on it, and the VCXO does not drift, then the system will continue to run with no adjustment made to the control line on the VCXO. If there is jitter on the reference, then the PLL will supply positive and negative pulses to the loop filter, to try to keep the VCXO tracking the reference. If the PLL is out of lock, then the PLL will be generating many pulses to try and drive the VCXO to the proper frequency. The lock detect circuit in the LMH1983 declares NOLOCK if the number of pulses sent out in a specified period exceeds a certain threshold. The LOCK_STEP_SIZE register specifies the period of time over which the LMH1983 counts pulses, and is measured in terms of Hsync pulses, the LOCK_THRESHOLD register specifies the maximum number of pulses that can be expected within this period and have the device still considered to be in LOCK. If the input signal has a lot of jitter on it, it is possible that the number of pulses will exceed LOCK_THRESHOLD, in which case NOLOCK will remain active, even though the PLL is remaining in a locked condition. What the datasheet is explaining on P28 is that to make the LOCK determination time the fastest, you load LOCK STEP_SIZE with a 1 (minimum amount of time to look at pulses) and LOCK_THRESHOLD with a 31 which is a large number, indicating that even if there is significant activity, the device should declare LOCK.
Note that the actual LOCK time is independent of the register settings, and it is possible to have the LMH1983 PLL1 locked to the reference, but because the reference has a lot of jitter, the conditions to actually declare LOCK may not be met. The register settings affect how fast and how sensitive the circuit which drives the LOCK indication are.
Thank you for the answer.I could clear it, however, please allow me to confirm one point.
There is a description on LOCK_THRESH.Does it specifies the number of clocks HIN pulses allowed timing validation?
“the LOCK_THRESHOLD register specifies the maximum number of pulses that can be expected within this period and have the device still considered to be in LOCK”.
Referring the description on the datasheet, it seemed to specifies the number of missing HIN pulsesallowed to stay in LOCKED.
“Sets the number of Hsync periods to wait before setting loss of lock. Since during blanking there can have up to 5 missing Hsync pulses, this value is usually set > 6.”
In later case, please let me know the timing window whitch determines the missing HIN pulse.
To assert LOCK (deassert NO_LOCK) the number of pulses driving the loop filter in a certain period of time (set by LOCK_THRESHOLD) needs to be less than a certain number, but also, there needs to be a reference present. To determine if there is a reference present, the device looks at the NO_REF. NO_REF is asserted if a period of time specified in register 27 goes by with no activity on the Hin pin. The period of time is set by two portions - of register 27, one portion is the number of Hsync periods, and the second is the number of additional 27MHz clocks to wait. Since for some formats, during blanking, there are 5 horizontal lines in which there is no Hin transition, usually the time period for the Loss of Reference Threshold is set to 6 Hsync periods. If more than this number of Hsync periods go by with no Hin transition, then the device declares NO_REF, and as soon as NO_REF is declared, NO_LOCK is also declared.
Thank you Mark-san.
I will close this question, however, pls allow me ask one more question.
The in the register table, Address 0x1B Bit[2:0] and Address 0x1C Bit[4:0]Have the exact same description.
"Sets the number of Hsync periods to waitbefore setting loss of reference. Since duringblanking there can have up to 5 missingHsync pulses, this value is usually set to 6."
Is the description on Address 0x1C bit[4:0] incorrect?
I will update the datasheet to make this more clear..
Address 0x1B, Bit [2:0] determines the number of HSYNC periods to wait before declaring a loss of REFERENCE
Address 0x1C, bit[4:0] determines the amount of time over which the device looks at loop filter activity to determine LOCK status.
Thank you for your reply.
I look forward to recevie the revised datasheet.
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