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Due to EMV constraints and our used display we can run the clock (TxClkin) only at 6MHz. The DS90C385AMT generally works with that frequency, but it is out of the specification (18 - 81.5 MHz). In some cases the display won't work as desired.
Are there alternative LVDS driver chips (sender and receiver) which can be run at lower frequencies? Any ideas why the DS90C385AMT doesn't work properly at 6MHz?
The DS90C385 has a PLL in it which generates the higher speed serial clock, and this PLL, as all PLLs, has a limited range over which it can lock. You may be able to get more reliable operation by multiplying your clock by a factor of 4 (to 24 MHz) and allowing the data to continue to change at the slower rate, then do a divide by 4 on the receive side.
In reply to Mark Sauerwald88474:
Thanks for your answer. We tried to run it with 18MHz and it worked technically, but we had EMV Problems with high frequencies and would like to run it slower. I just couldn't find any LVDS chips which can be used at lower frequencies.
In reply to David Liechti:
I am not familiar with the acronym 'EMV' - if it is interference that is troubling you, are you able to use the higher speed clock, but using a driver which has lower edge rates? - The LVDS side is unlikely to be causing much interference since the differential signals tend to be pretty quiet.
Sorry, I used the german acronym. I meant electromagnetic compatibility problems. Yes, a driver with lower edge rates probably would help. But the other problem is our display which is specified to work with up to 6MHz. It still works with 18MHz, but that's also out of specification, what we don't want...
Hi David, can you please share a block diagram of your system? Does your processor output 18-bit RGB video at 3.3V? Does it support 1.8V output? What resolution is your panel, and what data format does the panel receive? Does it receive LVDS, or are you using an LVDS RX device that sends RGB data to the panel?
The DS90C385 has an internal PLL and a specified PCLK FREQ range, running out of spec below the min is not guaranteed or supported.
There is a another part in the family with a lower min - you can try the SN75LVDS83B, which gets you down to 10MHz.
Perhaps system timing (increasing blanking) can be changed to boost the 6MHz PCLK to the guaranteed min rate.
SERDES devices with PLLs usually have specifed MIN and MAX PCLK frequency, operation outside that specified range is not recommended.
DPS APPS / SVA
In reply to RE:
- our processor does output 18-bit RGB at 3.3V.
- panel resolution: 240x320 pixel.
- the panel receives 18-bit RGB data at 3.3V.
- on the sender side we use the DS90C385AMT and on the receiver side we use the DS90CF386MTD.
- the panel's specification says that it can be run at 4-6 MHz, but it works without any problems up to 24MHz.
- we had massive EMC problems at higher frequencies, so we reduced the clock down to 6MHz (without properly checking the specs of the sender LVDS chip). Now, after producing 200 parts we have some cases where the display won't work anymore until the sender LVDS chip gets heated up a bit.
thanks for your help!
In reply to John Goldie:
Thanks for your tip. The SN75LVDS83B works at 10MHz, but the counter part (SN75LVDS82) only works with at least 31MHz. Is there a pin-compatible receiver available which also runs at lower frequencies?
The SN75LVDS83B is the lowest specified FlatLink (FPD-Link) SER we have, most of the discrete DES are speced at 20MHz min or higher. Some Displays with integrated DES in the TCON IC might support lower PCLK rates. The lowest 21-bit FlatLink-like DES is the DS90CR218A, it is speced at 12MHz PCLK rate. Being in the Channel Link (1) Family it can interoperate, but the output data is strobed on the RISING edge of the clock (not falling edge) - to retro that part in, either the TCON needs to be programable to latch on the rising edge or a fast invertor is needed to flip the clock polarity. To brute force in the FlatLink / FPD-Link parts into a low PCLK application (below spec) that would be about the only way to go and run at 12MHz.
Usually for the lower resolution panels / displays, there are other SERDES families that are more targeted for this application and have their PLLs centered for the lower ranges needed. Please also see the TI FlatLink3G series of parts - note PCLK is in the 3.5MHz to 26MHz range.
Another possible solution would be to revisit the EMC issues that were observed at 20MHz (min spec) - usually EMI issues are a function of edge rates more often than the switching rate. Perhaps additional waveshaping on the LVCMOS (a common trick) can filter down the emi if it is indeed due to the wide parallel RGB LVCMOS bus. RC filters have been used. Also investigate ground and applying more shielding if possible.
If you are interested in a full Ser/Des solution, the Channel Link II family has several devices that operate at a pixel clocks as low as 5 MHz. Since your gpu outputs 3.3V LVCMOS and your display requires LVDS, I would consider the DS92LV2411 and the DS92LV0412. Although these devices support up to 24-bit color you can simply tie off the unused bits.
This chipset will allow you to serialize all of your video and timing information down to a single differential pair or single ended signal. The LV2411 serializes the 3.3V LVCMOS data, while the LV0412 deserializes the data to LVDS. These devices also have features to directly fight EMI such as the serial data encoding and spread spectrum clock generation (SSCG) on the outputs of the deserializer.
Also, one advantage of serializing the data down to a single differential pair is that you can choose from a much wider selection of cables for your serial interconnect. It is much easier to find off the shelf shielded cables for a single differential pair than a closely phase matched shielded cable that you might use for the 83B or C385A. For example, you could connect the LV2411 and LV0412 with a standard USB2.0 cable.
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