Using Figure 7 in the data sheet I solved for the output impedance and I got an output of 1.85pF and 86 ohms. Is this correct? Also, I'd like to know how it changes with temp/supply voltage - either in value or the graph of Fig 7.
What is the actual threshold input?
What is the propagation delay vs input differential voltage (high to low and low to high)?
What is the actual short circuit output current. If you short the output to ground will you really draw 24mA or will it be less?
What is the offset voltage change with respect to load, temp, freq, supply voltage?
I determined the current source of this amp to be around 9mA-11.5mA, is this accurate?
What is the source of the voltage range provided in the data sheet? Is that really the current source varying under temp/supply voltage? What is the relationship between output drive and temp/supply voltage.
I don't know what to make of all the different variations of Vos. It seems by Fig 3 that Voc contains all the variations of Vos due to changes in logic state, but its only 150mV and the Vos steady state is 1V to 1.45V. So does this mean Voc can vary on top of the Vos range making a potential Vos range of <1V and >1.45 by 150mV? What is the maximum common mode voltage I can expect?
Does delta Vod increase the Vod output range or is the change contained within the listed min/max?
Based on the last two questions, what is the maximum output high voltage possible of this chip? My assumption (into 75ohms as the data sheet) is 1.45V+1/2*.475V = 1.6875V.
This device was characterized back in 2002, so it has been difficult to track down all the details on how the specs vary across different parameters. I have tried to answer all your questions to the best of my ability based on my knowledge of the device. My answers are in blue below:
Using Figure 7 in the data sheet I solved for the output impedance and I got an output of 1.85pF and 86 ohms. Is this correct? Also, I'd like to know how it changes with temp/input voltage - either in value or the graph of Fig 7.
The output impedance should be closer 50 Ohms, although I don’t know how tightly controlled that is. How are you doing this calculation? I don’t see how you are getting a capacitance value from Figure 7, since it does not have any timing information. The typical output capacitance of the device is 3 pF.
The input threshold level may vary from device to device and across operating conditions, but will not be greater than 100 mV.
What is the propagation delay vs input voltage (high to low and low to high)?
I am not sure how strong of a relationship there is between input voltage and propagation delay. The propagation delay through the device should be mostly due to the internal logic, though, which just requires that the input voltage exceeds the threshold value. There is about 25 mV of hysteresis on the switching thresholds, so inputs with a faster slew rate should have shorter propagation delays in general (if measuring propagation delays based on zero-crossings).
Yes, you will draw ~24 mA. It may be slightly less, but it should not be more.
What is the offset voltage change with respect to load, temp, freq, input supply voltage?
Across the full voltage and temperature ranges and across manufacturing process variations, the output offset voltage will vary between 1 V and 1.45 V.
The output voltage range is fairly large, so the current source value may not be very exact. Your range seems reasonable, though. A Norton equivalent that correlates to Figure 7 might be ~11.5 mA || 60 Ohm.
Yes, the output voltage will vary with the device’s current source value and output impedance. It will also vary with frequency, as shown in Figure 18. The output voltage range seems to be mostly due to manufacturing process variations, since with supply voltage and temperature fixed at their nominal values the output voltage can still vary from 285 mV to 440 mV (for 75-Ohm load). Accounting for voltage and temperature variance will widen the range to 270 mV to 475 mV.
The steady-state offset voltage will be between 1 V and 1.45 V. This range includes the difference in steady-state value you get in different logic states. On top of this steady-state range, there can also be a transient variation in the common mode. This is encompassed by the VOC(PP) spec, and is due to mismatch in rising and falling transitions. This peak-to-peak swing is superimposed on top of the steady-state offset range.
The min/max VOD spec encompasses the possible difference in VOD between logic states, so delta VOD does not extend the VOD range.
Your assumption is correct.
Please let me know if you have any additional questions.
Best regards,Max RobertsonAnalog Applications EngineerTexas Instrumentsmfirstname.lastname@example.org
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