TLK10002 Application Question

David,

Based on your description I am assuming you are using the TLK10002 in 2:1 mode for both channel A and B.  If this is the case, then the device will be able to support the data rate range from 500mbps to 4.5Gbps.  Note, that the device will not support 500mbps to 4.5Gbps in 4:1 mode.  As for reference clock, please see data sheet for valid reference clock range.   See table 4 in the TLK10002 data sheet for reference clock rates and respective line rates. Note, GHz reference clock rates are not supported.

In regards to HS PRBS verification,  I am not sure how HS verification will be done given that for each channel the 2 bits of LS data will be combined into a single serial  HS data stream.  I assume at you are looping- back HS_TX data streams to the HS_RX inputs and verifying LS_TX to LS_RX data streams.

The TLK10002 EVM guide with schematics is available online at: http://www.ti.com/tool/tlk10002evm

Please note the TLK10002 cannot be used at 4.5Gbps/ch in 4:1 mode.  In 4:1 mode, a maximum of 2.5Gbps line rate is supported for the LS inputs.

Thanks,

Atul Patel

Texas Instruments

Atul,

Thanks for your response. Let me elaborate on my needs further that way you can advice me on what can or can't be done on your end.

• A correct package drawing. I need this to begin the layout of my design
• A set of algorithms:
• For BER calculation
• For initialization and setting PRBS Error Counters
• Info if the ERROR COUNTERs have LOSS of LOCK and how many sequential bits are required to announce the lock or loss of lock
• Questions about the TLK10002
• What happens with Error counter if the count reached the maximum?
• What happens with counter if the pattern we have at input is not the pattern we are expecting?

David,

Just to confirm - are you planning on only using the device's LS side for pattern checking (i.e., the HS side and serialization functions are not needed)?  If so, are you using 4 lanes total (2 lanes of Channel A, 2 lanes of Channel B) or 8 lanes (4 lanes of Channel A, 4 lanes of Channel B)?

The package drawing can be found at the end of the datasheet.  This is the norm for TI datasheets.

To set up the LS side for PRBS error detection, here is what needs to be done:

1. Provision device for proper line rate, reference clock frequency, number of lanes, etc.
2. Enable test mode on LS input lanes by writing a '1' to bit 0x08.3.  (Note that the LS lane addressed by writes to register 0x08 is selected by bits 0x06.15:12.)
3. Select PRBS pattern length in bits 0x0B.5:4.
4. Enable LS test pattern verifier by writing a '1' to 0x0B.6.
5. Read error counter for desired LS lanes (registers 0x11 through 0x14).  Note that these registers will clear on read, so it is good to read them after enabling the verifier to reset them to 0.  The value returned by this first read operation should not be considered valid.

The error counters can then be read after a certain duration of time to calculate the BER.  The right duration will depend on the serial data rate, the BER target to which you are measuring, and the amount of confidence you need in the BER measurement.  For example, if the serial rate is 5 Gbps and you want to verify that the BER is better than 1E-12 with 95% confidence, you would need to read zero errors after about 10 minutes (3E12 bit times).  A good calculator tool can be found here: http://www.jittertime.com/resources/bercalc.shtml.

Regarding your question about a loss of lock - during normal device operation (receiving 8b/10b-encoded words), receiving a certain number of errors can trigger a loss of channel synchonization.  This causes the device to try to re-align its word boundary based on detection of the "comma" pattern.  There isn't any meaningful word alignment in PRBS test mode, though, so this feature is not used when the device is in test mode.  Errors are just accumulated in the error counter registers and do not cause any loss of lock.

Once the error counters reach their maximum value (0xFFFF), any additional errors will not be counted.  The counters will not "roll over" and show a lower value.  The value is cleared (set to 0x0000) after a read operation.

If the pattern received does not match the pattern being checked against, the device will detect many bit errors.

I hope this information is helpful.  Please let me know if there is anything else you need.

Best regards,
Max Robertson
SerDes Systems and Applications
Texas Instruments
m-robertson@ti.com

Max,

Thanks for your response. I do have a few more questions regarding my application and the TLK10002. To summarize, I have two applications where I hope to use the TLK1002. Both involve PRBS error detectors.

• For option 1, I plan to use 2 lanes of Channel A, 2 lanes of Channel B in LS side up all the way to 4.5Gbps. (each channel)
• For option 2, I plan to use 2 HS Channel A and B Rx inputs up to 9.0Gbps. (each channel)

Just to clarify the point about the mechanical drawing, I want to draw your attention to page 72 of the datasheet. The orderable part is TLK10002CTR, which comes in an FCBGA package. Page 73 shows the mechanical specifications for a PBGA package; therefore:

• Where can I find the mechanical data for the FCBGA package?

Returning to the operation of the TLK1002, it is my experience that some error detectors multiply the error count by 3.

• Does the TLK1002 allow for one-to-one error counting?

In addition, most PBS error counters start working after receiving a collection of bits (40/80/120/ect) to synchronize--and predict--the next bit of the PRBS sequence for error counting.

• What does the TLK10002 need to start error counting?

Lastly, what are the similarities/differences between the TLK1002 and the TLK6002 in terms of the error counting structure?

Again, thank you for your assistance. I look forward to your response.

-David

David,

There is only one package for this device, but I see what you mean about the naming conventions seeming inconsistent.  "FCBGA" (flip chip ball grid array) is an industry standard term for this type of package, and the corresponding JEDEC code is S-PBGA-N.  There are many different packages that can fall under these headings, though, so the relevant unique identifier is TI's package drawing code.  In this case, this is "CTR."  You'll note that the table on page 71 associates the orderable device TLK10002CTR with the package drawing CTR, and that the mechanical drawing on page 72 is titled CTR.

Regarding the PRBS error counting, it works by predicting what the current word should be based on the previously-received words.  It is possible, then, that a bit error in one word could cause false predictions in the next few future words and result in false error detection (e.g., the multiplier effect you mentioned).  To my knowledge this only occurs with the PRBS31 pattern, as there is a wait period implemented after error detection with the PRBS7 and PRBS23 patterns.

Another thing to keep in mind with the error detection is that it looks at several bits at a time, so if there are a few adjacent bit errors they may register as only one error in the counter.

Assuming that the receive link is up (i.e., enabled, PLL locked, and receiving enough data transitions for clock recovery), it will only take a few byte clock cycles for the PRBS verifiers to synchronize to the pattern and start making valid predictions.  This occurs much faster than MDIO read/write operations, so by the time the verifiers are enabled and the errors counters are cleared of their initial values the error detection should be valid. 

The error detection will operate the same way for both TLK10002 and TLK6002.

Best regards,
Max Robertson

Max,

Thanks for your help. I have one more question about the package. Because the website and the datasheet (page 71) reference the FCBGA package, will this be corrected? I just need to get a firm answer regarding this topic to reassure our component engineer that the official position from TI is that the TLK10002 comes in a PBGA package. I realize that in your earlier email you mentioned that his was simply an industry standard, but our components group needs something more concrete. I'm open to any suggestions you have, but in order for me to design with this part I need to address the inconsistency. I'm open to any suggestions you may have as well.

-David

David,

The different package names shouldn't be considered an inconsistency, since "PBGA" and "FCBGA" are not mutually exclusive terms.  The term "FCBGA" just means that the device uses flip chip assembly rather than bond wiring.  It doesn't say anything about the package material, which may be either plastic (PBGA) or ceramic (CBGA).  For reference, here is a list of the various FCBGA packages TI uses:

http://www.ti.com/sc/docs/psheets/type/fcbga.html

Note that this list contains both PBGA and CBGA packages.

Also, here is a list of the various PBGA packages that TI uses:

http://www.ti.com/sc/docs/psheets/jedec/s_pbga_n.html

Note here that there are many different package "types" listed: FCBGA, BGA (non-flip chip), FC/CSP (chip scale package), etc.  Since these different terms (PBGA, FCBGA, etc.) refer to different attributes of the same physical package, it is possible to use multiple terms without being inconsistent.  You'll see the "CTR" package designator show up on both the PBGA and the FCBGA list.

Best regards,
Max Robertson