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DS80PCI402/800 EEPROM programming

Guru 19775 points
Other Parts Discussed in Thread: DS80PCI402, DS80PCI800, DS80PCI800EVK, DS80PCI810

Please give us detail information how to program EEPROM.

As the meaning of each address and bits are not explained in detail, we can not start the design.

In the datasheet, we understand that there are "Table6: EEPROM Register Map - Single Device with Default Value "

and "Table 7: Example of EEPROM for 4 Devices using 2 Address Maps" as an example,

but, these information are not enough to designing the EEPROM settings.

  • Hi, it's a few years later (about 4), and I am now asking the same question, but with a little more zest.

    Table 2 does not define how to map the EQ bits (7:0) into the 3 bands of Boost. We need to understand how all 256 levels work.

    The Table 7, EEPROM single register map does not define many of the values stored in the EEPROM. We load the defaults listed in the example blindly.
    Table 9 lists in more detail, additional register functionality. However, table 9 does not map the bits that are stored in EEPROM back to the register offset/bit position in EEPROM/ Thus the column "EEPROM Bit" is relatively useless other than to let you know that there is persistent state that you are programming and you don't know how.

    In particular, the bits stuck between channels 3/4 and after channel 7 are completely a black hole. These are address bytes 0x15-0x16 and 0x24-0x27 in table 7.

    For example, I suspect that 0x26,0x27 may set the VOD/DEM for gen2 speed and the DEM/VOD registers that are documented set the DEM/VOD for gen3 speed, which is why it is suggested to set the DEM to 0 for gen3 so that the CLTE/linear amplifier passes the EQ from the real link partner TX to the ultimate RX device, but in gen2 mode it uses the fixed DEM/VOD from these secret registers.

    We have a basic group of settings functional, including an Address map with 4 slots, 4 devices, and CRC enabled. However, we would like to know we are done with the design. It's a bit of a crap shot to release this design to production without complete documentation.
  • Hi Stephen,

    Thanks for reviving the thread. Always good to try tying up loose ends.

    1. There are 4 EQ gain stages within the DS80PCI402/800. Each has two bits of resolution, hence a total of 8 total bits for control. While there are a possibility of 256 combinations, we have only been able to characterize 16 of these bits via simulation, and these are what is listed in Table 2. An image of the difference in these 16 EQ settings is shown below:

    ds80bst.pdf

    You are welcome to experiment with whether a combination of different bit settings for each stage yield better results when tuning the redriver. However, we do not have specific EQ CTLE gain values that are vetted by design simulation.

    2. Double checking...are you viewing the latest revision of the DS80PCI800 or DS80PCI402 datasheet (should be revised in 2015)? Both of these datasheets have the mapping of where the EEPROM bits are being taken from compared to the SMBus Slave Mode Register Map location. There is also more details about EEPROM mapping in the following app note: http://www.ti.com/lit/an/snla228/snla228.pdf

    If the corresponding SMBus Slave Mode register bits are marked as "Reserved," they should not be changed from their default values. The example in Table 7 uses the same values as the default.

    3. The EEPROM bits between Channels 3-4 are related to the signal detect behavior, explained in more detail when viewing Reg 0x28 of the Register Map in Table 9. EEPROM bits after Channel 7 should not be changed from default, as they are Reserved in the SMBus Register Map table (Table 9).

    4. We are happy to review your EEPROM .hex file to see if the settings make sense if you have it available. You can also use SigCon Architect in Demo mode and load in the .hex file within the EEPROM Page, then click "Load Device from Slot" to determine whether the settings you desire to use have been written correctly.

    Thanks,

    Michael

  • Michael,
    Thanks for the great solution! If you folks could add links for SigCon to the DS80PCI family devices, wow, I would have been a happy camper! Didn't know that sigcon even existed. (currently there are no links to any supporting software for any device in the DS80PCI family)

    I am using the latest datasheet, downloaded it from the web less than 3 weeks ago. It says SNLS324E, Revised Jan 2015.

    There are a couple of interesting points that should be documented in the datasheet. This would have saved me adding useless 2 pin headers.
    1) In SMBUS Master Mode, if there is a blank EEPROM, you can still access the EEPROM to program it.
    2) In SMBUS Master Mode, once the chips load their data from the EEPROM, you can access the device as a SMBUS slave.

    Note there is an errata in table 7, register offset 0x15. The Default value is listed as 0x09, but the detailed bit map documents 0x01. I used 0x09, as I believe that is the correct way to get the 1 in bit0 to load.

    I did use SNLA288 to help understand how to generate the map.

    If you can send me an email address, I will send you my config file. It supports 4 DS80PCI402, it's a gen3 x16 redriver (needs to do gen1 as well) that plugs into a motherboard and cleans up the lanes. The motherboard stretches the wires a tad too far with dielectric a tad too cheap, and uses a few to many vias on the link...
  • Hi Stephen,

    The SigCon Architect software is designed and tested only with our EVMs, so we can only ensure that the software works as expected with our EVMs. Thus, the link to SigCon Architect appears for the DS80PCI800EVK landing page as opposed to the IC landing page. However, you should still be able to use SigCon Architect with any other system as long as you have access to the SMBus SDA/SCL pins and another device is not taking control of the SMBus lines (assuming you are actively controlling the device).

    Regarding your requests:

    1. You can access a blank EEPROM no matter which mode you are in, but if you are in Master Mode, you will only be able to access the EEPROM if READ_EN# is not tied low. If READ_EN# is tied low, the redriver will take control of the bus, which will prevent you from programming the blank EEPROM and sending the redriver into an unknown state.  Is there a place in the datasheet that we have implied that you cannot access an EEPROM to program it when the device is in Master Mode?

    2.  We will add this request to our change list. We have made sure to note this in more recent device datasheets, such as the DS80PCI810 Master Mode description below:

    However, some of our updates in older generation datasheets do fall through the cracks. My apologies for that.

    Thanks for noticing the typo. That is correct. I believe what happened was that in our later devices, the value of Reg 0x28 in Slave Mode became 0x4C by default. This therefore changes EEPROM Offset 0x15 to 0x09 instead of 0x01. However, when we made our most recent update, it may have been a copy-paste from updated generation to older generation  Please keep the value of this set at 0x01. We'll add this to our change list, too.

    I'll send you an e-mail shortly, and we'll pick up the rest of the conversation offline.

    Regards,

    Michael