slla149-Refclk Jitter Analysis for the TLK2521

David,

Maximum allowed jitter for TLK devices is specified in Peak-to-Peak (PP) value. For 40ps PP jitter, this means the absolute deviation in position of any rising edge is no more than 20ps away from the ideal position of the rising edge. In other words, picture an ideal reference clock where every rising edge was precisely positioned so that clock period is constant and ideal. Now let each rising edge of this clock deviate from the ideal position of the rising edge by +/- 20ps. This is the kind of jitter we spec by 40ps peak -to -peak maximum.

Now in practice, we can tolerate much more jitter than 40ps peak-to-peak max on the reference clock under certain conditions. High frequency (like cycle-to-cycle jitter) can violate the 40ps max datasheet spec, and almost no degradation would occur. Low frequency wander of many hundreds of ps would be okay if the application is not affected by low frequency wander in the data stream. This is usually the case because the receiver will track out the low frequency wander anyway.

 It is reference clock jitter around the bandwidth of the PLL that is really the concern. As an example, the bandwidth of the TLK devices is in the neighborhood of 10MHz. Jitter components of the reference clock near the bandwidth of the PLL had better be under 40ps Pk-to-pk or our output jitter performance will suffer.  For this you will need to know the phase noise of the clock you intend to use for the application. Once you have the phase noise plot,  then you will be able to identify where in the frequency band most of the jitter resides.

Thanks,

Atul Patel

Atul Patel,

Thank You for your reply.

I do understand the fact that 40pS is relevant for the higher end applications and that the sensitivity for jitter is much higher in the pass band of PLL filter.

However my problems is that if we deal with a random jitter, the peak-peak value theoretically can be infinite.

In order to compare reasults of my measurements with your spec I have to know that I'm observing the clock over the same period of time as you did during your tests.

Regards,

David.

Hi David,

You are right that random jitter is theoretically unbounded, so any clock signal will have some chance of exceeding a “peak-to-peak” spec given a sufficient period of time.  This is why there is no such thing as a truly "error-free" serial link, and the goal of a designer is to restrict the probability of occurrence of errors to some low number.  This probability is the link’s bit error rate (BER), and common targets might be 10^-12 or 10^-15.

Since random jitter has a Gaussian probability density, it is possible to translate the “peak to peak” jitter spec into an RMS jitter spec if a BER is specified.  The BER is used to determine the allowable probability of a particular clock edge deviation from exceeding the error threshold (+/- 20 ps). 

For example, say you needed to ensure a bit error rate of 10^-12.  This means that 99.9999999999% of the clock edges need to fall within the 40 ps peak-to-peak spec.  Since this percentage of a normal distribution is bound by +/- 7.13 standard deviations, you can calculate the allowable standard deviation (RMS value) of the clock edge position as 20 ps / 7.13 = 2.81 ps (RMS).  If you need a tighter BER spec, then you would need a low RMS jitter value to reduce the probability of edge positions exceeding the peak-to-peak spec.  For example, if the BER target is 10^-15, you would need a +/- 8.03-sigma confidence interval.  This would give an RMS clock jitter value of about 2.5 ps.

Best regards,
Max Robertson
Analog Applications Engineer
Texas Instruments
m-robertson@ti.com

Thanks!

That helps.