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Question about the clock usage

Qipeng Cai1
Prodigy 20 points
Other Parts Discussed in Thread: TLK10002

Hello,


I have a question on the High-Speed SERDES in TLK10002.

Does HS SERDES have master mode and slave mode? I want to make clear which clock the Transmitter of HS SERDES uses. According to the datasheet, HS SERDES can internally provide two clocks:

1. the clock synchronized to the external reference clock -  VCO_CLOCK_x_DIV2
2. the clock recovered from the incoming serial data - HS_RXBCLK_x

Will the transmitter of HS SERDES always choose its clock temporal synchronized to the external reference? Or will it choose the clock according to the working mode? For example, it selects the clock synchronized to the external reference clock in master mode. However, it selects the clock recovered from the incoming serial data in slave mode.

Best regards,

Peter

  • 0
    TI__Mastermind 20820 points

    Hi Qipeng,

    The TLK10002 does not have a defined master mode or slave mode but you can think ofe its operation in this sens. The HS transmitter board will generate the master clock for the entire system and the the remote board receiving the HS signal will the slave. So the master board and slave boards will both start from their own local reference oscillator. This enables the PLLs to get going and the the device to operate correctly. Once the remote board starts receiving data, the HS recovered clock should be feed out of the TLK10002 to a jitter clear and then feed back into the second ref clock input on the device. This synchronous the entire system and can be done via software through your configuration file. The diagram below should help you understand this more: 

    http://e2e.ti.com/cfs-file.ashx/__key/communityserver-discussions-components-files/138/8103.TLK10002.pngRegards,

    Michael Peffers

    High Speed Interface Solutions

  • 0 in reply to Michael Peffers
    Prodigy 20 points

    Hello Michael,


    Thanks a lot for your explanation!

    I am still not clear how the slave board gets to know that the availability of the recovered clock. We know that the LOSx signal can be created by the combination of many different internal status signals, such as Loss of Signal and PLL Locked, etc. However, I didn't find any indicator for the availability of the recovered clock. Is Loss of Signal a good indicator for this purpose? I guess that the signal PLL Locked from HS interface is not a good one, because the PLL will lock to the local reference even the recovered clock is not available.

    To my understanding, the slave board needs an indicator for switching the reference clock from the local reference to the recovered clock. What is your opinion?


    Best regards,

    Qipeng

  • 0 in reply to Qipeng Cai1
    TI__Mastermind 20820 points

    Hi Qipeng,


    You are correct the slave board needs an indication of when to switch. The LOSx signal on the slave board is a good indication of when the recovered clock will be valid and ready to input as the new ref clock.

    Regards,

    Michael Peffers

    High Speed Interface Applications