We refer to the TI company's SD1983EVK evaluation board, use lmh1981 + lmh1983 to generate video&audio clock signal, of which 1981 for CVBS input sd composite video signal, the output 1981 H, V, F video sync signals are all normal, but these H, V, F sync signals give to 1983, by examining 1983 status registers and NO_LOCK,NO_ALIGN,NO_REF output pin, found 1983 no lock the input sync signal.The registers configuration of 1983 are all default. Read a part of the registers values are as follows: 0x00 = 12, 0x01=70,0x02=e0,0x05=2f,0x20=3f.
Why lmh1983 can't lock the input sync signal?Can you provide lmh1983 registers configuration information?