I am using the SN65LV1224B chip on the SN65LV1224BEVM board to decode LVDS data coming from a custom board with an FPGA on it. I am using a 27MHz oscillator has the REFCLK input. My LVDS data is being transmitted at serial rate of 128.4MHz(/12 = 10.7MHz parallel) . The deserializer Lock pin never goes low and the RCLK output doesn't show any clk output. I have tried sending the actual data I want to send, 0X000, 0x3ff, etc. I can see my LVDS signal on a scope and I am correctly sending the start and stop bits. I also tried a 10.519MHz clk as the REFCLK input and the chip would Lock for a few hundred ns and the unlock over and over. When the lock pin was low the RCLK out was at about 10.5MHz not the 128.4MHz clk the LVDS data was being transmitted at. Any help to resolve this issue would be appreciated.
What is the relationship between REFCLK input frequency and the frequency of the serial data. Does the REFCLK just need to be between 10MHz and 66MHz and it doesn't matter what the serial data frequency is?