DS90UB925Q datasheet (SNLS407C) describes : "The bit rates of any I2S bits must maintain one fourth of the PCLK rate". Does this mean if PCLK is 32MHz the I2S_CLK frequency must be 8MHz?
On the one hand, FPD-Link III application note (SNLA221) describes : "I2S_CLK frequency for DS90Ux92x devices must be maintained below PCLK/2 or 12.288MHz, whichever is lower."
For DS90UB925Q, can the I2S_CLK frequency be lower than PCLK/4? If PCLK is 32MHz can the I2S_CLK frequency be 1.411MHz?
Best regards,
Daisuke
