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[ DS90Ux925/6 ] I2C Communication Failure

Kenichiro
Mastermind 9165 points

[ DS90Ux925/6 ] I2C Communication Failure

Hi,
Can anyone help me to debug the I2C communication issue occurred on my customer board?
 Here is the summary.
In my customer system, each end has ASIC and CPU independently and they attempt to communicate each other via I2C interface as sequence above.
When ASIC and CPU are is master and slave respectively, ASIC try to write data to CPU twice, but "sometime" communication failure occurs in #3 step only with two different failure modes below.
 
Failure Mode 1
In this failure mode, it seems opposite side attempt to send ACK back to master side, but master side does not respond to it.
Failure Mode 2
In this mode, the data is not transferred (or not received correctly by opposite side).
It's greatly appreciated, if you can help me to understand...
* What condition can cause this failure?
* Which point I should check and take care to resolve this?
I'm not allowed to post all of data from customer, but if you contact to me directly,
I can share more data with you.
tanaka-k(at)clv.macnica.co.jp
Thanks,
Ken
  • 0
    TI__Genius 14015 points

    Hi Ken,

    Are you saying that I2C write commands to the same slave address, but with different data, is causing the failure? How often does this happen? Are the settings the same for both fail cases? 

    Is the 926 configured in I2C pass-through mode with the slave ID and alias ID set correctly? 

    Thanks,
    Jason

  • 0 in reply to Jason Blackman
    Mastermind 9165 points

    Hi Jason,

    Yes, you are right, this occurrs only on write to same slave with different data.

    Accoding to cutomer, this occurs during the car battery/accesasory voltage fluctuation test, but customer already confirmed that there is no voltage drop at the DS90Ux92x supply pins, since there are some regulatros in between.

    Also,occurence is really little, say, one or two time during few hundreds of trial.

    The situation is little complex, means both ends are designed by different tier-1 for same OEM. However I believe their setting such as IDs are well matched.

    Thank you for your support.
    Regards,
    Ken

     

  • 0 in reply to Kenichiro
    TI__Genius 14015 points

    Hi Ken,

    It's difficult to say what the issue is since the failure rate is so low. Here are some ideas:

    What are the I2C timing specifications of the CPU and ASIC? It's possible that they have custom timing that is different from the I2C specification. If that is the case, our devices have registers to adjust parameters such as Hold time and data output delay.

    Is it possible for them to connect the ASIC and CPU I2C buses directly and perform this test? If there are still failures, then that indicates the problem lies with those devices.

    Thanks,
    Jason

  • 0 in reply to Jason Blackman
    Mastermind 9165 points

    Hi Jason,

    Thank you for your comment, yes, it's not easy...so far we checked the power supply variation at VDD33 and VDDIO during test, but it seems no problem. Also we try to check some kind of sync signal such as VS, HS and LOCK, but as you aware, failure rate is low, not easy to catch.

    I will share more details once it's ready.

    Thanks,
    Ken