DS64BR401 Registers

Hi Mita-san,

I was able to investigate this issue for you in order to answer these questions. Please see responses below:

1. The default DEM value of 0x03 is correct. However, as you carefully observed, this is not a recommended value for DE control, because we cannot confirm that the output de-emphasis value that DE = 0x03 provides. When testing the device, do not use DE = 0x03 as a register setting. Select one of the 5 available register settings listed in the DEM table of the datasheet.

2. For RATE, the bit value is simply a way for you to select between a fast de-emphasis pulse width (1) and a slow de-emphasis pulse width (0). For rates that are 3 Gbps or less, setting RATE = 0 is sufficient. For higher SATA rates (6G), set RATE = 1. In most cases, it is recommended to set RATE = Float so that the device automatically determines the DE pulse width.

3. Auto Rate Mode is by default controlled by the pins. If you leave RATE, TX_IDLE and SD_TH pins = Float, the device will behave in auto rate mode. If you want to use registers to control this behavior, you will need to override the pin settings in Reg 0x08. I also believe that the datasheet has a mistake and that the default behavior in the registers is for Auto Rate and Auto Idle . I have confirmed with the DS80PCI402 (which has a similar register map) that a value of 0 = Automatic and 1 = Manual Override, so Auto Rate mode is actually the default.

4. The DS64BR401 default value settings are not recommended for use in SATA applications. I think all you will need to do to start with is to change the EQ and DE optimization settings while keeping other automatic detection settings like RATE, TXIDLE and SD_TH as floating.

I will work on generating a .nrd file to you in the next hour that matches the default configurations indicated in the "Recommended SMBus Register Settings" section of the datasheet. During testing, please only use EQ and DEM values suggested by the datasheet.

Thanks,

Michael

Hi Mita-san,

Please refer to the attached files for ALP .nrd file information. I have attached three files:

6505.ds64br401_default.nrd

- ds64br401_default.nrd: Default startup values taken from live DS64BR401EVK device on bench (via  DS64BR401 ALP Profile).

7220.ds64br401_datasheet_default.nrd

- ds64br401_datasheet_default.nrd: Complete set of default register values from 0x00-0x4E upon startup taken from live DS64BR401EVK on bench

3010.ds64br401_recommended.nrd

- ds64br401_recommended.nrd: This is a .nrd file set with the recommended SMBus settings according to the example on p. 16-17 of the DS64BR401 datasheet.

The EQ, VOD, and DEM settings may need to be optimized from the ds64br401_recommended.nrd file, but it will serve as a starting point for tuning.

Thanks,

Michael

Hi Michael-san,

Thank you for the answers. I am working with Mita-san on this application.

We have additional question for default DEM setting in SMBus mode.

[Question]
Could you please tell us the detail operation for DEM value = 0x03 ?

When DS64BR401 is powered up at SMBus mode, the device will operate in this mode until the register is written to the recommended value.

Customer needs to make sure that there would be no problem at power up.

Best Regards,
Kawai

Hi Kawai-san,

During development of the DS64BR401, it was discovered that when ENSMB = 1 (SMBus Mode) and PWDN = 1 (Low Power Mode), setting either the DEM[2] or DEM[1] values to 1 leads to undesirable current coming from our part. This problem only occurs when ENSMB = 1 and PWDN = 1, and the fix we implemented requires that we keep DEM[2:1] = 00'b and use the recommended datasheet settings for de-emphasis. Therefore, regardless of whether the device is operating in power-up (PWDN = 0) or power-down (PWDN = 1), performance remains intact.

Assuming PWDN is not asserted as 1 initially upon power up, the default DEM setting of 0x03 should not present issues, and it theoretically is designed to provide -3.5dB de-emphasis. However, in order to operate the device appropriately to handle the situation when ENSMB = 1 and PWDN = 1 mentioned above, we strongly recommend using the settings listed in the register map table of the datasheet for programming DEM.

Thanks,

Michael

Hi Michael-san,

Thank you very much for the information. Please let me confirm about your answer.

[Q]
What do you mean by DEM[2] and DEM[1] ?
Is it a typo for DEM[1] and DEM[0], pin setting ?
Or, is it the register setting of the DE control address bit[1:0], not bit[2:1]  ?

[Q]
I understand that if DEM[1:0]=00'b, there would be no undesirable current as DEM[1:0] pin setting does not have "1" for its setting.
If the pin setting should be DEM[1:0]=00'b the default register setting should be 0x01 instead of 0x03 which is shown in the register map. Why was the value 0x03 chosen for this default value ?

Thanks and Best Regards,
Kawai

Hi Kawai-san,

I double-checked our notes and DEM[2:1] is correct, not DEM[1:0]. For example, for CH0, Reg 0x11[2:1] must be zero in order to avoid this undesirable current when PWDN = 1 and ENSMB = 1.

The value of 0x03 was used in the original digital design, and this issue of the undesirable current was only discovered during bench evaluation after the digital design and defaults were finalized. Therefore, in order to resolve this issue, we needed to use the digital default values that were already in place and find an appropriate way to program the desired amount of de-emphasis. These settings we recommend are the ones that are listed in the DS64BR401 datasheet.

Thanks,

Michael

Hi Michael-san,

Thank you for your prompt reply. I understood that DEM control address bit[2:1] must be set to 00'b.
Please allow me to ask you additional questions.

[Q]
However, the default value "0x03" is 00000011'b which bit1 = "1". So do you mean there is an undesirable current flowing at the default power up with PWDN=1 and ENSMB=1 ?

[Q]
What is the current amount [mA] which would flow in this mode ?

[Q]
If the user continued using the device with DEM Register = 0x03, what would happen ?
Would the device get damaged ? Is there any impact ?

[Q]
Does DS64BR111 also have the same problem ?

Thanks and Best Regards,
Kawai

HI Kawai-san,

Please see responses below:

1. Yes, that is correct. However, the PWDN pin is typically connected to an input that is logic-low to indicate that an endpoint or ASIC is present. Therefore, in normal operation should be PWDN = 0.

2. The current in this situation is on the scale of 120 mA rather than <10 mA.

3. This problem seems to manifest itself whenever the situation of PWDN = 1 and ENSMB = 1 occurs. As long as PWDN = 0, there should not be any issue. However, there are concerns over the larger current and electromigration in this case that can lead to shortened device life. Please do not use DEM = 0x03 if you can program to any of the other recommended options in the datasheet.

4.  The DS64BR111 uses a digital design similar to the current 2-channel repeaters (DS80PCI102, DS100BR111, etc.). It does not exhibit the same issue.

Thanks,

Michael

Michael-san,

I am clear. I greatly appreciate for the detail information.

Best Regards,
Kawai