DS110DF410 / register 0x1E bits 7:5

Hi Kato-san,

The reg 0x1e, bits[7:5] control the output signal, by default it is set to 0x7 (mute - when no signal is present or when the retimer is unlocked). When the CDR is locked, the output is retimed data. Changing just this reg 0x1e does not affect the CDR from achieving lock. In order to force the output to be the desired signal shown in table 9 of the datasheet (eg, mute or retimed or raw), the reg 0x09, bit 5 needs to set to 1.

Regards, Michael

Michael - san,

Thank you for the reply. If we set the reg 0x1e[7:5] to 0x1 and the reg 0x09[5] to 0x1,  is CDR easy to be acheived lock ?

Because our customer could acheive lock by changing the reg 0x1e[7:5] to 0x01. I have attached our customer's configuration text.

(X"FF", X"0C"),  -- #ADR 0xFF = 8'b00001100 = 0x0C
(X"00", X"04"),  -- #ADR 0x00 = 8'b00000100 = 0x04
(X"FF", X"0C"),  -- #ADR 0xFF = 8'b00001100 = 0x0C
(X"15", X"54"),  -- #ADR 0x15 bit[6], bit[2:0]
(X"2D", X"84"),  -- #ADR 0x2D bit[2:0]
(X"31", X"20"),  -- #ADR 0x31 bit[6:5] = 2'b11(Mode3)
(X"36", X"30"),  -- #ADR 0x36 bit[5:4] = 2'b11
(X"08", X"00"),  -- #ADR 0x08 bit[4:0] = 5'b01100
(X"0B", X"0F"),  -- #ADR 0x0b bit[4:0] = 5'b01001
(X"2F", X"24"),  -- #ADR 0x2F bit[7:4] = 4'b1110
(X"36", X"31"),  -- #ADR 0x36 bit[2:0] = 3'b101
(X"09", X"00"),  -- #ADR 0x09 bit2 = 1
(X"18", X"40"),  -- #ADR 0x18 bit[6:4] = 3'b001
(X"60", X"00"),  -- #ADR 0x60 = 0x00
(X"61", X"00"),  -- #ADR 0x61 = 0x99
(X"62", X"00"),  -- #ADR 0x62 = 0x00
(X"63", X"00"),  -- #ADR 0x63 = 0x99
(X"64", X"00"),  -- #ADR 0x64 = 0xFF
(X"0A", X"1C"),  -- #ADR 0x0a = 0x1C
(X"DD", X"00"),  -- #ADR 0xDD = 0x00
(X"0A", X"18"),  -- #ADR 0x0a = 0x18
(X"1E", X"29"),  -- #ADR 0x1e = 0x29 ->TX MUTE OFF

Best Regards,

Kato

Hi Kato-san,

I took a look at the configuration.txt file and am a little confused about whether the correct bits are being written. I assume that the second set of hex values are what is written to the register (first set of hex values).

If this is the case, it appears that the device is not being written correctly. Please correct me if I am reading this configuration text incorrectly for the following lines:

(X"31", X"20"), -- #ADR 0x31 bit[6:5] = 2'b11(Mode3)
(X"36", X"30"), -- #ADR 0x36 bit[5:4] = 2'b11
(X"08", X"00"), -- #ADR 0x08 bit[4:0] = 5'b01100
(X"0B", X"0F"), -- #ADR 0x0b bit[4:0] = 5'b01001
(X"2F", X"24"), -- #ADR 0x2F bit[7:4] = 4'b1110
(X"36", X"31"), -- #ADR 0x36 bit[2:0] = 3'b101
(X"09", X"00"), -- #ADR 0x09 bit2 = 1
(X"18", X"40"), -- #ADR 0x18 bit[6:4] = 3'b001
(X"60", X"00"), -- #ADR 0x60 = 0x00
(X"61", X"00"), -- #ADR 0x61 = 0x99
(X"62", X"00"), -- #ADR 0x62 = 0x00
(X"63", X"00"), -- #ADR 0x63 = 0x99
(X"64", X"00"), -- #ADR 0x64 = 0xFF

The notes on about what ADR bits are being written do not match what is in the parentheses, so I want to double-check that, for example, Reg 0x64 = 0xFF and not 0x00.

As Michael-san mentioned above in this thread, changing Reg 0x1E to output retimed data will not affect the speed at which CDR lock occurs. CDR lock time is improved by using Ref Mode 3 in order to incorporate the external 25 MHz reference clock. 

Regarding your customer's use of Reg 0x1E = 0x29 on the last line of the file, the configuration text thus far still does not allow the user to override the desired output signal. You must set Reg 0x09[5] = 1. The comments in the configuration text imply that the customer is setting Reg 0x09[2] = 1.

Thanks,

Michael

Michael - san,

Thank you for the reply. I comfirmed the configuration with customer.

The comments in the configuration text isn't correct.however, write command is correct.

・write command (*I delete the comments in the configuration text.)

(X"FF", X"0C")
(X"00", X"04")
(X"FF", X"0C")
(X"15", X"54")
(X"2D", X"84")
(X"31", X"20")
(X"36", X"30")
(X"08", X"00")
(X"0B", X"0F")
(X"2F", X"24")
(X"36", X"31")
(X"09", X"00")
(X"18", X"40")
(X"60", X"00")
(X"61", X"00")
(X"62", X"00")
(X"63", X"00")
(X"64", X"00")
(X"0A", X"1C")
(X"DD", X"00")
(X"0A", X"18")
(X"1E", X"29")

Customer believes that CDR lock time is faster by setting (1EH,29H).

By the way, please let me know how long it takes to be achieved CDR lock after incoming singal in the worst case.

The setup condition is using Ref Mode 3 and the external 25 MHz reference clock.

Best Regards,

Kato

Hi Kato-san,

Thanks for your patience as we looked deeper into this issue. After consulting with the designer, we have the following feedback about Reg 0x1E functionality:

Reg 0x1E[7:5] corresponds to the output multiplexer, as indicated in the datasheet. However, Reg 0x1E[7:5] serves two functions. It depends on whether the output mux is set before CDR lock or after CDR lock.

Before CDR Lock, the channel is muted by default. After CDR Lock, the channel outputs retimed data by default.

1. Before CDR Lock: Setting Reg 0x1E[7:5] will override the default behavior. The default behavior of Reg 0x1E[7:5] is mute, so before CDR lock, the channel output will be muted unless otherwise specified. However, even if you set Reg 0x1E[7:5] = 001'b (retimed data), the output is invalid noise. The data output can only be valid once the retimer channel CDR achieves lock. Therefore, it is possible to see the output of a channel where Reg 0x1E[7:5] = 001'b sooner than when the output of a channel where Reg 0x1E[7:5] = 111'b, but in both cases, the data is only valid once CDR lock is asserted.

2. After CDR Lock: Setting Reg 0x1E[7:5] will only override output multiplexer if you set Reg 0x09[5] = 1 (Override Output mux). Therefore, in this case, Reg 0x1E[7:5] becomes an override output mux for situations after CDR lock, not before.

In summary, setting Reg 0x1E[7:5] at start-up will configure the output mux BEFORE CDR lock (though any output data you see is unreliable since CDR is not locked), and setting BOTH Reg 0x1E[7:5] and Reg 0x09[5] will configure the output mux AFTER lock. I believe what may be giving the impression of a faster lock time is that the customer is seeing output data at startup when they set Reg 0x1E[7:5] = 001'b, but this output does not correspond with reliable data until CDR lock is achieved.

The typical condition for lock time in Ref Mode 3 is ~10-15 ms. I do not expect the worst case to take more than several more ms to lock. If operating in Ref Mode 0, the lock time can take around 1 second, and it is possible that false-lock to spurs or a non-optimized frequency.

Hope this helps!

Thanks,

Michael

Hi Michael - san,

Thank you for the detailed explanations.

I understood setting reg 0x1E[7:5] at start-up will configure the output mux before CDR lock, and when customer set reg 0x1E[7:5] = 001'b, the lock time for the output is faster than reg 0x1E[7:5] = 111'b.

I have one more question.

Customer is seeing an lock indication pins, LOCK_0,LOCK_1,LOCK_2 and LOCK_3. In this case, Are LOCK_* pins  also faster just like the outputs ?

Best Regards,

Kato

Hi Michael - san,

we are looking forward to your response.

I kindly ask you for your ongoing support.

Best Regards,

Kato

Hi Kato-san,

The LOCK_n pins should not be faster, regardless of whether you set Reg 0x1E[7:5] pre-lock or post-lock. I have confirmed with digital design that internally, configuring Reg 0x1E[7:5] has no effect on the timing by which LOCK status will assert.

The customer is likely to see data pre-lock, as previously mentioned, but the data is meaningless until lock is declared.

Hope this helps!

Thanks,

Michael