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Jitter or some effect by switching 3G-SDI(HD/SD) signals from SFP+ or LMH0387 using TS3DV642

Hirotaka Matsumoto
Guru 27525 points
Other Parts Discussed in Thread: TS3DV642, LMH0387

Hi all,

Would you mind if we ask TS3DV642?

Our customer wants to switch 3G-SDI(HD/SD) signals from SPF+ or LMH0387 using TS3DV642.
(Please refer to attachmentfile.)
5280.0361.5025.Construction.pdf

On this construction, according to using TS3DV642, we have following questions.

<Question>
1. Is it possible to construct the system like as attachmentfile?
2. And then, if it is possible, what should we notice?(Jitter, some effect)
3. Location of AC-coupling capacitance
    －We found on the data sheet that it recommends that AC-coupling capacitance should be placed at output side(D0 +/-).
       On the our customer case, does it say the same?

Please let know us these.

Kind regards,

Hirotaka Matsumoto

  • 0
    TI__Guru* 76130 points

    Moving to the correct forum.

  • 0 in reply to Elias Villegas M.
    TI__Mastermind 45350 points

    1. Is it possible to construct the system like as attachmentfile?

    No it is not possible to construct the system like the attached file because you will run out of switches in the TS3DV642.  The TS3DV642 is a 12 channel 1:2 mux meaning it can only handle 6 differential pairs.  In the attached file it appears that there will be 8 differential pairs going into the TS3DV642 device.  System connectivity does not have a single chip solution to cover 8 differential pairs but maybe another group in TI can comment if they have a switch that can accommodate in a single chip.

    2. And then, if it is possible, what should we notice?(Jitter, some effect)
    You will see some insertion loss in the signal due to the on resistance. 

    3. Location of AC-coupling capacitance
        －We found on the data sheet that it recommends that AC-coupling capacitance should be placed at output side(D0 +/-).
           On the our customer case, does it say the same?

    From page 4 in the datasheet, "Note that the TS3DV642 is not designed for passing signals with negative swings; the high speed signals need to be properly DC biased (usually ~1V from the graphic controller side) before being passed to the TS3DV642."  I'm not sure what customer requirements of the signal are but this device requires a DC offset to avoid negative voltage swings.

    Adam

  • 0 in reply to Adam Torma
    Guru 27525 points

    Adam san,

    Thank you for your reply!

    And then we apologize that our information makes you confuse.
    Please refer to attachmentfile.
    5756.20140922_Construction.pdf

    With Including above attachmentfile, we'd like to ask you follwing questions again.

    1. Is it possible to construct the system like as attachmentfile?
        This is the construction like as the datasheet's TS3DV642. 
        It means that 4 differential pairs switched  A-side or B-side. 

    2. Location of AC-coupling capacitance
        4 differential pairs are DC biased, and after TS3DV642, there are AC coupling capacitances.
        (At inputs of FPGA,  differential pairs are with +DC biased.)
        Is our understanding correct?  

        Please let know us.

    Kind regards,

    Hirotaka Matsumoto


  • 0 in reply to Hirotaka Matsumoto
    TI__Mastermind 45350 points

    Hirotaka

    1. Is it possible to construct the system like as attachmentfile?  Yes the configuration in the attached file is valid.    This is the construction like as the datasheet's TS3DV642. 
        It means that 4 differential pairs switched  A-side or B-side. 

    2. Location of AC-coupling capacitance
        4 differential pairs are DC biased, and after TS3DV642, there are AC coupling capacitances.
        (At inputs of FPGA,  differential pairs are with +DC biased.)
        Is our understanding correct?  Yes all signals through the TS3DV642 need to be DC biased to avoid negative swing through the switch. 

    Page 4 of the datasheet," Note that the TS3DV642 is not designed for passing signals with negative swings; the high speed signals need to be properly DC biased (usually ~1V from the graphic controller side) before being passed to the TS3DV642."

     

    Adam

  • 0 in reply to Adam Torma
    Guru 27525 points

    Adam San,

    Thank you for your reply.

    The configuration is valid, and there are some insertion losses in the signal due to the on resistance.  
    PortA at DC: -0.75dB
    PortB at DC: -1.00dB

    If our recognition is incorrect, please let know us.

    Hirotaka Matsumoto


  • 0 in reply to Hirotaka Matsumoto
    TI__Mastermind 45350 points

    Your recognition is correct.

     

    Adam