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DS90UB913A/914A HS/VS

toshi-e2e
Genius 4705 points

Hi all,

1. Does DS90UB913A accept below HS/VS signal when 10-bit High-Frequency mode is set?
    During Blanking period, there is no HS signal.

　　　

2．Also, could you please explain about below specification?
    What does it become in a timing chart? 

 "10-bit High-Frequency mode: HS restricted to no more than one transition per 10 PCLK cycles."

Regards,
Toshi

  • 0
    TI__Genius 13475 points

    Toshi

    The data inputs are sampled on each PCLK and those data bits are encoded onto the FPD-III words which are being sent out.   HSYNC and VSYNC are much lower bandwidth, and therefore do not need to be sampled and transmitted as quickly as the other data bits.   This results in the restriction to have no more than one transition every 10 PCLK cycles.   If you want to send a high bandwidth signal across the link, you may be able to do so using 12 bit mode, and using the extra two data bits to transmit the timing information.

    Mark

     

  • 0 in reply to Mark Sauerwald88474
    Genius 4705 points

    Hi Mark-san,

    Thanks for your reply.
    I understand.

    Regards,
    Toshi