This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DS90UB925 TX to UB928

Other Parts Discussed in Thread: DS90UH928Q

Can someone please confirm for me that the DS90UB925 Serializer/Transmitter is compatible with the DS90UB928 receiver?

  • Hi Randy,

    The DS90UB925 is compatible with the UB928.  The GPIOs are mapped differently but all other functionality is normal.

    Regards,

    Mike

  • There is a GPIO errata when using DS90Ux928 DES with the DS90Ux925 SER
    Note: This errata is not relevant when using the DS90Ux928 DES with DS90Ux927 SER
    The errata listed below describe known cases where the DS90UH928Q device performs
    differently than specified in the datasheet description. Recommended workarounds are
    provided where applicable.
    1. GPIO0 (pin 14)
    Description: 925 GPIO0 (pin25), when programmed as an input, does not map
    out on 928 GPO0 (pin 14), when programmed as an output; this is
    the SER to DES direction.
    Note: When 928 GPI0 is programmed as an input and 925 GPO0 is
    programmed as an output, 925 GPO0 is mapped correctly; this is the
    DES to SER direction
    Work-around:
    Option 1:
    Use 925 GPO_REG4 (pin 43), this will map to 928 GPIO0 (pin 14)
    a) Set DS90Ux925 in 18-bit mode by mode pin = 1 or by register
    0x12[2]=1
    b) Set DS90Ux928 register 0x1D[0]=1 and 0x1D[2]=1; this will enable
    GPIO0 as output
    c) Set DS90Ux925 register 0x0F[0]=1 and 0x0F[1]=1; this will enable
    GPO_REG4 as input
    Option 2:
    If only a static signal is needed, use 928 register 0x0D[3] (GPIO0
    OUTPUT VALUE). When 0x0D[3]=1; GPIO0 will be a static HIGH.
    When 0x0D[3]=0; GPIO0 will be a static LOW. This register can be
    written remotely from 925 or locally from 928
    Option 3:
    Use another available GPIO.
    Status: Datasheet will be modified to correctly reflect this behavior.
    2. GPIO1 (pin 26)
    Description: 925 GPIO1 (pin26), when programmed as an input, does not map
    out on 928 GPIO1 (pin 13), when programmed as an output; this is
    the SER to DES direction.
    Note: When 928 GPIO1 is programmed as an input and 925 GPIO1 is
    programmed as an output, 925 GPIO1 is mapped correctly; this is the
    DES to SER direction
    Work-around:
    Option 1:
    If I2S_DB ((pin 44) is not being used, then:
    Use 925 GPO_REG5 (pin 44), this will map to 928 GPIO1 (pin 13)
    a) Set DS90Ux925 in 18-bit mode by mode pin = 1 or by register
    0x12[2]=1
    Errata Rev 1_1 Texas Instruments Confidential 8/21/2013
    b) Set DS90Ux928 register 0x1E[0]=1 and 0x1E[2]=1; this will enable
    GPIO1 as output
    c) Set DS90Ux925 register 0x10[0]=1 and 0x10[1]=1; this will enable
    GPO_REG5 as input
    Option 2:
    If only a static signal is needed, use 928 register 0x0E[3] (GPIO1
    OUTPUT VALUE). When 0x0E[3]=1; GPIO1 will be a static HIGH.
    When 0x0E[3]=0; GPIO1 will be a static LOW. This register can be
    written remotely from 925 or locally from 928
    Option 3:
    Use another available GPIO.

    GPIO2 and GPIO3 map correctly in both directions.

  • Hi Mike,

    My application is RGB888 which means pin 25 of the UB925 is used for pixel data. Can you please confirm that if I am using RGB888 video, that the UB928 will output the full RGB888 in its output LVDS video stream?

    Thanks,

    Randy Holmberg

  • Hey Randy,

    The UB928 will output the full RGB888.  See the image below for the mapping of the bits into the LVDS stream.  There are two options depending on the state of MAPSEL on the UB928.

  • Mike,

    One more question - can you please let me know what is the range of values for the built in pull-down resistors on the input data lines? The reason I ask is that the FPGA driving this has built in pull up resistors to VDDIO that can be on the order of 10K ohms. If the Pull-Down resistors built into the UB925 are on the order of 2K ohms, then I can guarantee that all of the input data lines are low when the FPGA is in configuration and the PDB pin is low.

    Thanks,

    Randy Holmberg

  • Hey Randy,

    The UB925 uses active pull-downs with a nominal drive strength of ~500nA. We recommend for best design practice to implement an external pull-down resistor as well.

    Regards,

    Mike

  • Hi, TI My customer wants to use the Work-around: Option 1: method . Does TI guarantee the " Work-around: Option 1" usage ? And do you have a plan to add the document to the Data sheet ? I'd like to confirm the Eratta 's validity.