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DS90UB914A-CXEVM: deserializer configuration through I2C

Other Parts Discussed in Thread: DS90UB914A-CXEVM

We are using the DS90UB914A-CXEVM evaluation board. We want to configure the deserializer registers through I2C but we don't get to access to these registers. The  I2C address of the deserializer by default in the evaluation board is supposed to be 0x60 and we are using the I2C peripheral master of a Zynq platform in the Zedboard evaluation board. We connect the SDA, SCL, VREF (3.3 V) and GND from the Zedboard to the DS90UB914A-CXEVM I2C interface.

We don't know if it is something wrong in the configuration: the signal levels? the connection to the board? the I2C address? the I2C signals? something in the board configuration?

Any suggesstion?


Thank you very much in advance.

  • Hi Ainhoa,

    Please check to ensure that your pullup resistors are 0 Ohm on the deserializer EVM. A slave address of 0x60 corresponds to zero resistance on the IDx[0] and IDx[1] lines.

    Also, please check your SCL and SDA line pullup resistors. We recommend 4.7 kOhm for both of these lines.

    Lastly, our devices are capable of operating at an SCL clock frequency of 400 Kbps (fast mode) or 100 Kbps (standard mode). Please make sure that you are operating at one of these speeds.

    -Sean
  • Hi Sean,

    Thank you very much for your fast response.

    I've checked all points that you comment and it seems to be OK.

    The SCL clock frequency is of 100 Kbps. The SCL and SDA line pullup resistors are 4.7 KOhm (these resistors are in the DS90UB914A-CXEVM board).

    In the deserializer datasheet, it is said that the I2C Master must support clock stretching. I'm not sure if this can be a problem. For example, how to know if the Zynq I2C peripheral supports this behaviour and what happens if the I2C Master does not support it. Could it derive in a communication problem when the first ACK is processed?


    Ainhoa
  • Hi Ainhoa,

    In order to verify that the I2C master supports clock stretching, you would need to check the user's guide/datasheet for the Zynq I2C peripheral. If the I2C master does not support it, then you will inevitably receive I2C communication errors. Clock stretching simply means that the slave device (in this case, DS90UB914A) will hold the SCL (clock line) low until it has processed the transaction requested by the master (in this case, Zynq peripheral). The reason for this behavior is because there will be latency from when the master sends out its first request to when it receives an answer back from the slave. If this latency is longer than the time between the master sending out its first and second requests to the slaves, then there would likely be timing errors because the master will not receive the answer back to his first request from the slave before the second request is sent.

    Also, when you address the slave I would also try using address "0xC0" instead of "0x60". Some master devices will address the slave using the full 8 bits of the address instead of only the most significant 7 bits.

    -Sean
  • Hi Sean,

    Thank you very much for the information. At the end, I achieved to communicate with the deserializer through I2C using the 0xC0 address. 

    I had another problem related to the serializer configuration through I2C. I try to explain this issue:

    If I connect the I2C master to the DS90UB913A-CXEM board, I can communicate without any problem with the serializer through I2C. However, I want to connect the I2C Master to the DS90UB914A-CXEM board and the DS90UB914A-CXEM board is connected to the DS90UB913A-CXEM board through coaxial cable. In this scenario, I don't achieve to access to the serializer I2C slave.

    I need that this scenario works because our final objective is to configure through I2C a image sensor (I2C slave) connected to the  DS90UB913A-CXEM board  whereas the I2C master is connected to the DS90UB914A-CXEM board. First, we have to configure the image sensor and then the image sensor generates the PCLK signal which will be the clock for the serialization and deserialization of the image data. Is this behaviour possible? What do I have to do in order to send I2C signals over the coaxial cable without PCLK signal?

    I hope that you understand my problem.

    Thank you very much in advance.

    Best regards,

    Ainhoa

  • Hi Ainhoa,

    Your setup makes sense. In order to configure I2C access for the 913A EVM board (and later the remote I2C sensor) you will need to do a few things:

    1. Ensure that your I2C Master (i.e. microprocessor) supports clock stretching. The 913A and 914A chipsets already support this functionality as stated in the datasheet, although your I2C master must support it too for remote I2C access. Also, ensure that your I2C image sensor (I2C slave) supports clock stretching as well. This will be needed in your final configuration if you are trying to communicate over coaxial cable from the I2C master to this device which is a remote I2C slave.
    2. In order to write to the 913A remotely, you will need to setup a slave alias on the 914A to communicate. For example. write the data "0xB0" to register 0x07 (SERID) on the 914A deserializer. This will allow remote I2C communication.

    -Sean