DS90UB913,4A-Q1 / PLL Lock time at the temporary stop of PCLK input

Hello Ryuji,

1) No, as you mentioned in your waveforms there is a PLL lock time associated with the incoming data on the 914A side.

2) The PLL deserializer data lock time will still be approximately the same. This value is listed between 15 -22 ms (typical - maximum). Looking at Figure 17 in the datasheet, it would only be slightly less than the lock time on startup because the PDB pin has already reached VDDIO. The same formula applies for the PLL lock time on the serializer which will still be in the range of ~1-2 ms even after PCLK is stopped temporarily.

-Sean

Hi Ryuji,

Are you sure that this is the data lock time on the 914A side? The lock time for the PLL on the 913A to sync to the incoming LVCMOS inputs is ~1-2 ms and much closer to the 3.7 ms that your customer is seeing.

How is your customer measuring the lock time on the deserializer? This time should be from the PDB reaching a voltage of VDDIO/2 to the LOCK pin asserting high.

-Sean

Hi Ryuji-San,

The datasheet is slightly confusing because the lock time mentioned for 914A which is 12-15 ms is really the power-up to
LOCK delay which as you know was stated previously as the time taken from PDB = VDDIO/2 until LOCK = HIGH. The main point
to note here is that valid LVDS data is constantly being streamed in over R_IN+/-.

There is a more specific definition of "lock time" which is the time from the LVDS data on R_IN+/- becoming valid to the
LOCK pin rising HIGH. This ASSUMES that PDB = HIGH already and this lock time is actually much less than the power-up to LOCK
delay described above. The 3.7 ms that your customer is seeing for LOCK time (with PDB = HIGH and PCLK restarted) is
a typical measurement one would expect to see and there is no need for worry.

I believe the reason why this difference in LOCK time is hard to see with the PDB transition from VDDIO/2 to VDDIO is
because Figure 12 in the datasheet is not necessarily drawn to scale in regards to the start-up timing of the PDB pin.

Best regards,
Sean

Hi Ryuji-san,

Testing this on a bench in the lab, the LOCK delay should very close to 3.7 ms in testing on our 913A/914A EVM's. This would be a typical condition.

Unfortunately, we cannot provide a maximum condition as reference data because this would need to go through characterization like all of the datasheet conditions that we test for.

The correlation here makes sense because measuring the LOCK time from PDB going HIGH will be a much longer time compared to waiting for valid data on RIN+/-. This is because the deserializer device is still booting up during and after the ramp of the PDB pin, whereas this is not the case when the system is waiting on valid data to be received over the link and both Ser/Des devices have already been ON for a long time.

Hope this helps Ryuji-san.

Sean