DS90UB913A PDB reset pulse width

Hello Toshi,

Assuming that the power supply ramp has been completed (VDD_IO and VDD_n have settled at their steady-state values), we do not spec the minimum pulse width because this will depend on the customer's path to GND to drive the PDB pin from 1 to 0 to reset the system. If the customer has a low DC impedance path to GND (~ 1 Ohm) then a pulse width > 1 ms is a conservative recommendation to ensure the 913A device is reset.

We also recommend putting 10uF capacitor in series with a 10k resistor on the PDB input pin. This corresponds to R*C = 100 ms PDB startup delay upon device power-up.

-Sean

Hi Sean,

You seem have confusion. The customer just want to know a minimum effective pulse width to enter the power down state as a reset state which caused by the PDB pin “1” to “0” signal level.

Why the customer wants to know the minimum effective pulse width for the PDB pin is they not want to enter the power down state during operating condition by something accident as to pull down the PDB pin by very small width pulse noise or glitch noise. If they will know the width, probably they will put a something filter which is based on the minimum effective pulse width. Without the value it’s impossible to avoid such situation in the customer. I think if internal circuit of the PDB doesn’t have a filter which can eliminate very small width pulse noise or glitch noise, the value should be very small as less than few ns or more small.

Could you check the value? Without the value the customer can’t enter mass production, so we need your help.

Best regards,

Izumi Maruyama