Hi
I have the TLK2711 SerDes on my board. I wanted to test it with the loopback feature.
At the moment I don't have a real data to send, so I took the GTX clock (coming from the FPGA) at 100Mhz
and started to divide it by two to generate clocks as data (meaning that D0 is a 100Mhz/2=50Mhz clock, D1 is 100M/2^2=25Mhz clock and so on up to D15 is 100M/ 2^16 = 1525Hz clock).
I shifted the derived clocks to verify the GTX 100Mhz clock will rise at the middle of the "data" clocks.
I activated the Enable/ Rx_EN/ LPEN pins, verified the MSB/ LSB K/ D bits are low (Data bytes) and I have noticed that signals started to appear on my FPGA input bus pins (and no more signal on the TX serial pins).
Problem is that the received signals, after the loopback, where not the transmitted fixed clocks, but rather they looked like real data, meaning all variations of pulses width.
Is it the expected result from such "data"?
Why don't I get the fixed clocks as my Rx data?
Thanks
Amnon