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TLK2711-SP jitter requirement

Other Parts Discussed in Thread: TLK2711-SP

Hi everyone,

I am currently doing some preparatory work for a memory unit testing design and we plan to use the TLK2711-SP in combination with an Xilinx Spartan 6 FPGA. For providing the reference clock to the TLK2711-SP we have two possibilities:

1) Direct connection of  a Silicon Labs Si570 I2C Programmable XO Oscillator to the TLK2711-SP reference clock input.

 Si570 -->  TLK2711-SP

2) Connection of  Silicon Labs Si570 I2C Programmable XO Oscillator to the Spartan 6 (internal Delay Locked Loop) and output to two TLK2711-SP.

 Si570 --> Spartan 6 (DLL) ----> TLK2711-SP

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--> TLK2711-SP

 

The reference clock timing requirements stated in the data sheet TLK2711-SP say: "Jitter: peak to peak max. 40 ps". Now my question is what type of jitter is this? Is it period jitter, cycle-to-cylce jitter or time interval error? And what part of the jitter is included in this value? Is it 40ps of periodic jitter + random jitter?

 

best regards,

Florian

 

 

 

 

  • Hi Florian,

    Maximum allowed jitter for TLK devices is specified in Peak-to-Peak (PP) value. For 40ps PP jitter, this means the absolute deviation in position of any rising edge is no more than 20ps away from the ideal position of the rising edge. In other words, picture an ideal reference clock where every rising edge was precisely positioned so that clock period is constant and ideal. Now let each rising edge of this clock deviate from the ideal position of the rising edge by +/- 20ps. This is the kind of jitter we spec by 40ps peak -to -peak maximum.

    Now in practice, we can tolerate much more jitter than 40ps peak-to-peak max on the reference clock under certain conditions. High frequency (like cycle-to-cycle jitter) can violate the 40ps max datasheet spec, and almost no degradation would occur. Low frequency wander of many hundreds of ps would be okay if the application is not affected by low frequency wander in the data stream. This is usually the case because the receiver will track out the low frequency wander anyway.

    It is reference clock jitter around the bandwidth of the PLL that is really the concern. As an example, the bandwidth of the TLK devices is in the neighborhood of 10MHz. Jitter components of the reference clock near the bandwidth of the PLL had better be under 40ps Pk-to-pk or our output jitter performance will suffer. For this you will need to know the phase noise of the clock you intend to use for the application. Once you have the phase noise plot, then you will be able to identify where in the frequency band most of the jitter resides.

    Regards!
    Luis Omar Morán Serna
    High Speed Interface Group
    SWAT Team