DS90Ux92x I2S MCLK

Toshi

Hi,TI I'd like to con firm the MCLK function . The application Report(SNLA221) said that " If I2S CLK frequency is less than 1MHz, this feature has to be disabled....." IS it a jitter issue ? My customer want to use I2S_clock as 352KHz(22KHz, 16bit mono)

over 8 years ago

0 Toshi over 8 years ago

Expert 1780 points

Could you please answer the question ? I d like to know the MCLK limitation and is it OK to use a I2S_clock as 352KHz(22KHz, 16bit mono) ?

0 Naomi Sugiura42 over 8 years ago in reply to Toshi

TI__Intellectual 1820 points

Kobayashi-san,

Since the PLL needs to be disabled for I2S clock frequencies below 1 Mhz, the jitter will be higher at I2S_clock= 352 KHz.

Best Regards,
Naomi Sugiura

0 Toshi over 8 years ago in reply to Naomi Sugiura42

Expert 1780 points

Sugiura-san, I see, thank you.

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DS90Ux92x I2S MCLK