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LMH1980 - t_HSOUT timing when using tri-level sync with steep transition

Kawai
Guru 19775 points
Other Parts Discussed in Thread: LMH1980

Hi Team,

The rise time of tri-level sync signal for 1080i is normally f=0.054us. The datasheet defines t_HSOUT as 525ns(TYP).

However, our customer would have a tri-level sync signal with very steep rise time f=0.00675us.

Could you advise us how t_HSOUT timing would change in this case ? They require HSOUT timing information for this condition.

Thanks in advance.

Best Regards,

Kawai

  • 0
    TI__Mastermind 32575 points

    It will decrease by about 48 ns (delta of the input rise time conditions for standard and non-standard timing).

    Alan

  • 0 in reply to Alan O
    Guru 19775 points

    Hello Alan-san,

    Thank you for your help. I am thinking that td_HSOUT would be longer than the value in the datasheet.

    I am understanding the slice level of LMH1980 is +70mV from sync chip. I believe that actual HSOUT output timing is based from this slice timing. However, the definition of td_HSOUT is from 50% of the tri-level sync. So, I think the HSOUT timing from 50% level td_HSOUT would be longer (increase) when the rise time is much steeper. Could you give me your opinion ?

    Best Regards,

    Kawai

  • 0 in reply to Kawai
    Guru 19775 points

    Hello Alan-san,

    Could you please help us on this ?

    We do understand that this kind of abnormal tri-level sync signal is not supported for the device.

    However, it would be helpful if you could provide us the information how the device is designed for HSOUT output timing.

    Does "Sp" of the tri-level sync signal (upper part) relating to the HSOUT output timing ?
    From customer evaluation, HSOUT output timing seems to be based from this part.



    Best Regards,
    Kawai

  • 0 in reply to Kawai
    Guru 19775 points
    Hello Team,

    Could anybody help us supporting this device ?

    It would be helpful if you could tell us how the HSOUT output is generated (HSOUT output mechanism) inside LMH1980.

    Best Regards,
    Kawai
  • 0 in reply to Kawai
    TI__Mastermind 32575 points

    Hi Kawai-san,

    Sorry for the delay.  I was out of office all last week, and could not respond.  Mita-san also alerted me to your inquiries.

    For SD bi-level sync input, the sync slicing is done 70-mV above the falling edge of the negative-sync tip.  However, it is different for a tri-level sync input.

    For HD tri-level sync input, it is true that the the sync slicing is done on the input's rising edge (not the falling edge of negative-sync tip).  I believe the sync slicing point is on the rising edge between the zero-crossing level and the positive-sync tip level, and auto-adapts to the tri-level sync tip amplitude if there is a double-terminated (sync levels = +/-150 mV) or unterminated  (sync levels = +/-600 mV) conditions.

    This explains why the HSOUT prop delay measurement value is effectively lower when the input tri-level sync rising edge is faster than the HD standard timing (which the datasheet is specified for).

    Regards,
    Alan

  • 0 in reply to Alan O
    Guru 19775 points
    Hello Alan-san,

    We greatly appreciate for your support.

    Is it possible to confirm the designer what is the actual sync slice threshold level for the tri-level sync signal ?

    Best Regards,
    Kawai
  • 0 in reply to Kawai
    TI__Mastermind 32575 points
    LMH1980's input clamp the sync-tip bottom to a fixed voltage and sense the sync tip. From that it calculates the detection threshold. For tri-level sync, it is sliced on the rising edge at 75% of the tri-level sync amplitude from the negative sync tip. From the tri-level sync tip diagram from earlier (Tue, Jul 7 2015 8:39 AM), this corresponds to the Sp/2 level of the positive sync tip. Since it is percentage based, it is adaptive level (not fixed) to handle improper sync amplitudes / termination condition.

    Regards,
    Alan