Hello I have the following problem. I need to deserialize the video stream from DS90UH925Q serializer (HDCP is disabled) and I have to use the DS90UB948-Q1 deserializer becuse of future compatibility with DS90UB947.
The video stream from UH925 has PCLK frequency 16 MHz that is too low, because UB948 needs 25 MHz - 96 MHz (in datasheet).
But when I connect them together the UB948 LOCKs and streams out the deserialized data...unfortunately the data seems to be wrong. HS, VS, DE signals consists of more transitions than they should and sometimes carries a random data. So I try to find out if the problem is in my FPGA (that deserializes the 8 diff pairs from UB948) or the UB948 sends a bad data.
My question: "Is possible that UB948 streams out a wrong data although it is LOCKed ? But LOCKed at lower frequency that is allowed in the datasheet."
Thank you.
Ondra
