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DS90CR287 - Incorrect TX CLK OUT waveform

Kawai
Guru 19775 points
Other Parts Discussed in Thread: DS90CR287

Hello Team,

Our customer is facing a problem that Tx CLK OUT of DS90CR287 is strange compared to the datasheet Figure 16. They observe waveform such like below in red. Incidence rate is not so high. I have confirmed that they have correct power up sequence that they have valid clock input for CR287 before de-asserting /PWR_DOWN pin. Do you have any idea why  Tx CLK OUT is abnormal ?

Thanks in advance.

Best Regards,

Kawai

  • 0
    TI__Genius 13475 points
    On the DS90CR287 the Transmit clock is received, and it goes to a PLL which multiplies the frequency by a factor of 7, the TXCLK signal has the first 2 sevenths of the cycle high, then three cycles low, followed by an additional 2 cycles high. If your PCLK has a large amount of jitter on it, it may be the case that the PLL is sometimes correcting and losing one of the 1/7 cycles, resulting the the PCLK waveform that you are seeing. I am assuming that the cycle with only 2/7 being low is not a steady state, but rather a single cycle that is occaisionally observed.
  • 0
    TI__Expert 3050 points
    Hi Kawai-san,

    Please confirm your customer's clock frequency. The DS90CR287 is intended to operate from 20 to 85 MHz. Operation outside of this range is not supported.

    Also, please confirm with a scope shot that the LVCMOS clock and data meet the VIH and VIL requirements in the datasheet. Note that VIL min = GND. LVCMOS signals that exceed these limits can cause problems with the PLL.


    Mike Wolfe
    DPS APPS / SVA
  • 0 in reply to Mike Wolfe
    Guru 19775 points
    Hi Mark-san, Mike-san,

    Thank you for your prompt response. We are also considering the PCLK jitter, PLL power supply voltage and power supply noise spec.
    I will ask customer to check these requirements again and see if the issue reproduces.

    Their clock frequency is 37.125MHz and their VIH/VIL level had no problem.

    Best Regards,
    Kawai