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Alignment of TLK10232

ttd
Mastermind 7660 points
Other Parts Discussed in Thread: TLK10232

 

 Dear Technical Support Team,

 I have question about TLK10232.

TLK10232 has four low speed input lanes(XAUI RX). If one lane's input becomes indefinite after linkup and established connection, does TLK10232 cause misalignment at XAUI Lane Alignment?

I think that LOS(loss of signal) causes at first, then I think that failed lane will be resynchronized at own Channel Synchronization Block(Page12 Figure 3-2.).

But I don't know the behavior of XAUI Lane Alignment at this time.

For example , Dose XAUI Lane Alignment keep previous correct alignment? And dose "XAUI Lane Alignment" insert some data(idle signal?) for failed lane to keep link of High Speed TX?

Best Regards,

y.i

  • 0
    TI__Genius 16150 points
    Hi y.i,

    Basically, XAUI is a full duplex interface that uses four (4) self-clocked serial differential links in each direction to achieve 10 Gb/s data throughput. Each serial link operates at 3.125 Gb/s to accommodate both data and the overhead associated with 8B/10B coding.
    For that reason, the TLK10232 implements a special lane alignment scheme on the low speed (LS) side for 8b/10b data that does not contain XAUI alignment characters.
    During lane alignment, a proprietary pattern (or a custom comma compliant data stream) is sent by the LS transmitter to the LS receiver on each active lane. This pattern allows the LS receiver to both delineate byte boundaries within a lower speed lane and align bytes across the lanes (2 or 4) such that the original higher rate data ordering is restored.
    Lane alignment completes successfully when the LS receiver asserts a “Link Status OK” signal monitored by the LS transmitter on the link partner device such as an FPGA. The TLK10232 sends out the “Link Status OK” signals through the LS_OK_OUT_A/B output pins, and monitors the “Link Status OK” signals from the link partner device through the LS_OK_IN_A/B input pins. If the link partner device does not need the TLK10232 Lane Alignment Master (LAM) to send proprietary lane alignment pattern, LS_OK_IN_A/B can be tied high on the application board or set through MDIO register bits.
    So, if one lane is indefinite, you are going to get a "wrong" signal at high speed side of TLK10232.

    I hope this helps.

    Regards!
    Luis
  • 0 in reply to Luis Omar Moran
    Mastermind 7660 points
    Hi Luis,

    Thank you for your quick reply.
    I understand your explanation of aliment. By the way , I think that this explation is basen on General Purpose mode.
    Datasheet desclibese that LS_OK_OUT_A/B is valid in 10G General Purpose Serdes Mode.

    ■datasheet page7 "Table 2-1. Pin Description - Signal Pins"
    Valid in 10G General Purpose Serdes Mode.
    LS_OK_OUT_A=0: Channel A link partner transmit lanes not aligned.
    LS_OK_OUT_A=1: Channel A link partner transmit lanes aligned.

    How can we check "XAUI alignment" status in XAUI to 10GBASE-KR transceiver?
    I don't find it on datasheet.

    Best Reagards,
    y.i
  • 0 in reply to ttd
    TI__Genius 16150 points
    Hi y.i,

    You can check "XAUI alignment" status through register:
    CHANNEL_STATUS_1 ==> DA: 0x1E RA: 0x000F
    LS_ALIGN_STATUS Bit [14]

    I hope this helps.

    Best Regards!
    Luis