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Guidance after damaging SN65LVDT388ADBT inputs.

W. David Lee
Prodigy 120 points

I'm sending data to various daughter boards from my Zynq FPGA using LVDS25 configuration on its IO pins. I send the LVDS pairs over Samtec ribbon cables with 0.025 inch pitch. The cables vary in length from 6 inches to 9 inches for different boards.

On the daughter boards, I use the SN65LVDT388ADBT LVDS receiver chip. Everthing was working fine until I came across 1 board that had a failed fresh out of the bag from my contract manufacturer. The input resistance of the of the AB pairs was low. Here are the resistances for the first 4 pairs I'm using (Ohms): 5, 11, 16,  15. This is measured powered off with cable removed. The value measured on a known good chip is 95 Ohms.

When I power up the system, these low input impedances pull down my LVDS signals and no one is happy.

So, I replaced the chip and it happened again! The channels that I use on the chip have developed low input resistance. (The unused, unconnected channels are 95 Ohms).

I really, really don't think it is ESD. (I use good anti-ESD practices). The design is super-simple and many of these boards are working just fine.

The FPGA outputs might all go to high impedance, +2.5V or GND when it is booting up.

Any thoughts on how I could be blowing these inputs?

Cheers,

David

  • 0
    TI__Guru* 98485 points
    Hello David,

    Can you tell me anything about your termination scheme? Do you have termination resistors close to the receiver inputs on the SN65LVDT388ADBT? It seems like you are saying that you can semi-reliably reproduce the issue so do you have a means to probe the voltage and or current at the differential inputs during the damaging event?

    Best Regards,
    Casey McCrea
  • 0 in reply to Casey McCrea
    Prodigy 120 points

    Hi Casey,

    Thanks for the reply. Oops, I thought that the SN65LVDT388ADBT had internal 100 Ohm terminations and that was all I needed.

    Basically, I've added nothing to the LVDS data path except for Samtec connectors and cables.

    I am starting to suspect some wild transients in common mode voltage as the daughter card and FPGA boards power up off their independent supplies.

    Do you think a TVS diode arrangement at the inputs to the SN65LVDT388ADBT would help with ESD and power startup transients? I'm thinking of something like the ESDR7534.

    I'll try to measure the startup transients today.

    Cheers,

    David

  • 0 in reply to W. David Lee
    TI__Guru* 98485 points
    David,

    You are correct that with the built in 100 ohm termination you do not need additional termination. I wanted to make sure the device was not doubly terminated. It seems likely to me that startup transients could be the problem as you say, but it would certainly help to see some measurements. If this is the case, a TVS diode array could help. I can take a look at your measurements later today.

    Regards,
    Casey McCrea
  • 0 in reply to Casey McCrea
    TI__Guru 62910 points
    Hi David,

    One other thing I wanted to add to this discussion is that the internal termination resistance of the 'LVDT388A can be damaged when the voltage across it exceeds 1 V (per the absolute maximum rating table). While this wouldn't be expected during normal operation when receiving ~350-mV LVDS signals, is it possible that larger voltages are present at start-up? For example, if the "A" and "B" lines coming out of the FPGA become configured at slightly different times (leaving one at ground, for example, while the other is at its steady-state offset value), etc.?

    Best regards,
    Max
  • 0 in reply to Max Robertson
    Prodigy 120 points
    Right on Max.

    I think you're on to something. Also, I am completely dissatisfied with how I've handled the power up sequence of the daughter cards vs FPGA.

    David