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DS90Ux947/948 OpenLDI input spec

Hi TI, I'd like to confirm the OpenLDI input spec of DS90Ux947. Is it possible to input a 170MHz CLK + single OLD(LVDS X 4) to DS90Ux947 input ? (Off course, the device can be operate under dual FPD-LinkIII mode.) If it possible, please let me know the input strobe spec of OLDI(skew margin) ?
  • Toshi

    When operating in single link mode, the device is limited to 96MHz PCLK.

     

  • Mark-san, Thank you very much for your replay. well, I'd like to confirm again, does the device work under 170MHz CLK + dual OLD(LVDS X 8) ? It should be 9.52Gbps(4.76Gbps FPD-LINKIII X 2), I guess it's impossible. Could you please explain the meaning of "Dual Link: Up to 170MHz Pixel Clock" in the Features ? I'd like to know the maximum PCLK input frequency? under single OLDI( and dual FPDLINKIII mode).
  • Mark-san, I'd like to send more simple question. Does the device has the following function, Single OLDI input ---> Dual FPD-LINKIII outputs(Odd,Even) ?
  • The device can operate in either of two modes: In single link mode, a pixel clock in the range of 25MHz to 96MHz may be applied, as well as 4 data lines. Each data line carries 7 bits so the total bandwidth that is being transported is 2.7Gbps. The actual clock frequency on the CLK inputs is 1/7 of the pixel clock rate. In dual link mode, all eight input pairs are used, and there is a single CLK input - the pixel clock frequency in this mode is 170MHz, and the actual frequency of the PCLK going into the device is 1/14 of this frequency. In dual pixel mode, the output of the deserializer consists of two ports, each with four data lines and one CLK. The two modes cannot be intermixed (single pixel transmitter to dual pixel receiver).
  • Mark-san, I see, thank you for your help.
  • Hi Mark,
    I am wondering the same question. your initial reply seems to be in direct conflict with the DS90UB947 datasheet that states:
    "OpenLDI Clock Frequency (Single Link)" has a minimum frequency of 25MHz and a maximum frequency of 170MHz.
    Under "Feature Descriptions" it mentions "OpenLDI clocks" are limited to 96MHz in single "lane" mode and limited to 170MHz in dual "lane" mode where "lane" seems to refer to the differential outputs of the DS90UB947 device. Please verify if the datasheet is incorrect.

    Regards,
    Jason