This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LMH1983 USER DEFINED MODE

Other Parts Discussed in Thread: LMH1983, LMH1981

I'm planning to have use a mux between the LMH1981 H,V,F signals and a word clock input H (48K,96K,192K), Ground V, Ground F.  I read some posts that the LMH1983 won't be able to autodetect without V & F?


The other question I have is needing to determine registers 0x51 - 0x5D for user defined mode to detect 192K word clock.  Can you please provide information as to what internally these registers are set to for 48K & 96K to help me determine what their values should be for 192K?


Thanks,

Brian

  • Hi Brian,

    You are correct LMH1983 needs HVF to correctly detect incoming video format. LMH1983 looks at the 27MHz clock pulses and V&F to determine incoming format.

    With respect to your 2nd question, are you saying you have 192 KHz clock and you want to LMH1983 to genlock to this clock? You are supplying this clock or 48Khz or 96KHz clock? Please clarify and i will look into this.

    Regards,,nasser
  • Nasser,

    I need clarification on the first part.   If I want to just feed a 48 KHz,  96 KHz, 192 KHz word clock into the LMH1983, it seems like I only need to feed that into H and I ground V & F and it should auto detect this?  The data sheet implies this on page 20.  

    I want to use a user defined mode to detect a 192 KHz word clock.    To do this I need to configure registers 0x51 - 0x5D.   It would be helpful for me to know the values of these registers for 48KHz and 96 KHz to help me determine what I should set    .  Thanks.

  • Hi Brian,

    1). For format codes 0-24 we need to use V&F. For other codes, 25-30, we can use just HSYNC and ground V&F(to prevent spurious signals).

    2). You can enable auto format detection and genlock to 48KHz or 96KHz and then read look up table registers 0x51-0x5D.
    Also, you can disable AFD 0x05[5]=0 and force the desired format 0x20[5:0]. These would enable you to genlock to either 48 or 96KHz and then read register 0x51-0x5D as well.

    Regards,,nasser
  • Nasser,


    2)  If I do as you instructed (0x05[5]=0, select desired format 0x20[5:0], and genlock to 48K), registers 0x51-0x5D will represent the values used internally for 48K?


    As I mentioned, I'm trying to figure out what 0x51-0x5D are set to for 48KHz and 96KHz to help me determine what the values should be for 192KHz.

    Thanks,

    Brian

  • Hi Brian,

    You are correct after forcing the selected format , 0x20[5:0] and 0x05[5]=0, first make sure you are genlocked to the desired rate and then read registers 0x51-0x5D.

    Regards,,nasser
  • Hi Nasser,


    To test what you suggested, I input a blackburst signal into the LMH1981 and read registers 0x51-0x5D and they were all 0's.  Any other suggestions for finding out the values of 0x51-0x5D for 48KHz and 96KHz?  Any way you can give me a call?

    Thanks,

    Brian

  • Nasser,

    It appears to me that obviously the part has values for 0x51-0x5d to use for the autoformat modes but they are not updated in 0x51-0x5d. I'm trying to find out what those values are for a 48KHz and 96KHz word clock.

    Thanks,
    Brian
  • Hi Brian,
    After forcing the format to lock to 48KHz for example i thought you should use 48KHz clock as input to HSYNC input. In this case HSYNC is running at 48KHz. Also, please confirm PLL1 is locked before reading 0x51-0x5D. Also, please note i am on a trip and my responses would be delayed.

    Regards,,nasser
  • Nasser,

    I have an LMH1981 with H,V,F connected to LMH1983 through a resistor pack. To test what you said, I connected a blackburst source to the LMH1981 and read 0x20 to make sure the format was recognized. I then read 0x51-0x5D and they read all 0's.

    I wanted to try the above experiment before removing the small resistor back and injecting 48KHz into the Hsync and grounding V & F.

    I didn't read anything in the manual about 0x51-0x5D showing the values for what it is genlocked too. Are you sure that is correct?

    Thanks,
    Brian
  • Hi Brian,

    Registers 0x51-0x5D are the user defined registers. If you want to read settings the device uses please read the following registers: 

    1). Divisor setting 1: 0x29, 0x29 16 bits read

    2). Divisor setting 2: 0x2B, 0x2C 16 bits read

    3). Charge pump: 0x28

    4). TOF1 count: 0x3B,0x3C 16 bits read

    5). Input code: 0x21

    5). TOF4 Settings: 0x49

    6). Interlaced indication: 0x00 bit 7.

    Please note i am traveling at the moment and responses would be delayed.

    Regards,,nasser

  • Nasser,


    That helped but I have some follow-up questions:

    1. How to determine 0x51-0x54?  I know how to determine the nominal but not high and low values.  I was hoping to figure out the 48KHz and 96KHz high and low values in order for me to figure out the 192KHz values.  I have no idea how much margin to give this with high and low.

    2. Charge pump 0x28 is a 5-bit value and 0x59 is an 8-bit value.  Don't understand that.

    3. Charge pump 0x28 says default value is 01000.  Does that change with autodetect or never changes?

    4. What is 0x5D bits 3:0?

    Thanks,

    Brian

  • Hi Brian,

    I am traveling at the moment. Next week when i am back in our lab i am planning to look into this question. This is the first time i see a need to genlock to 192KHz signal and we need to write to custom registers.

    Regards,,nasser
  • Nasser,

    I was hoping there would be some more internal documentation about the LMH1983 that you might be able to reference.  I'm pretty sure I can get this to work but I'm more worried about reliability.  Please read especially 1 below.

    1. Registers 0x51-0x54.  There are 11250 27MHz cycles in 20 Hsync periods for 48KHz, 5625 27MHz cycles in 20 Hsync periods for 96KHz, and 2812.5 27MHz cycles for 192KHz.  It would be nice to know what the settings are for 0x51-0x54 for 48KHz and 96KHz to help me determine the margin for 192KHz.  For example for 192KHz, should I set the max to 2813 and the min to 2812?  Should I set the max to 2818 and the min to 2807?  I'm not sure and knowing what they are set to internally for 48KHz and 96KHz would make this decision very easy.

    2. Charge pump 0x28 is a 5-bit value and 0x59 is an 8-bit value.  Don't understand that.

    3. Charge pump 0x28 says default value is 01000.  Does that change with autodetect or never changes?  What is it for 48KHz and 96KHz?

    4. What is 0x5D bits 3:0?

    Thanks,

    Brian

  • Nasser,


    Any chance on an answer to my last post? 


    Thanks,

    Brian

  • Hi Brian,

    Please first setup the device to lock to 48KHz and 96KHZ and read the following registers. 

    0x27[4:0] = ICP1 charge pump(PLL1 charge pump) current when fast lock is active

    0x28[4:0] = ICP1 charge pump current when fast lock is inactive

    (0x29, 0x2A) [9:0] = R divisor

    (0x2B, 0x2C) [14:0] = N Divisor

    (0x3B, 0x3C) [12:0] = # of lines per frame format(LPFM)

    0x21[3:0] Input vs code Look up table pointer

    0x49[7:0] TOF4_AFS

    0x00[7] = Interlace status

    The above registers are the settings LMH1983 uses for PLL1 configuration. In the user custom mode similar register specify the same settings at different register addresses. Please note for 192KHz you can use the same value as above for the following registers? USR_TOF1_LPFM, USR_IN_VS_CODE, USR_ICP, and USR_TOF4_AFS

    (0x51, 0x52)[15:0] = High value of range for custom user mode(USR)

    (0x53, 0x54)[15:0] = Low value of range for USR mode

    (0x55, 0x56)[9:0] = USR_DIV_R1 R divisor for custom mode

    (0x57, 0x58)[14:0] = USR_DIV_N1 N divisor for custom mode

    0x59[7:0] = USR_ICP 192KHz charge pump current. You can use the same value as either register 0x27 or 0x28

    (0x5A, 0x5B)[12:0] = # of lines per frame format. Please use 0x01 for this register(the same value used for 48 and 96KHz)

    0x5C[7:0] = Please use the same value as TOF4_AFS = 0x01

    0x5d[4] = USR_Interlaced. Use the same value used for 48 and 96KHz = 0x00

    0x5d[3:0] = Input vs code look up table pointer. Use the same value as 48 and 96KHz = 0x08

    Please use 2812+5 for high and 2812-5 for low range. These are the tolerances we have for 48 and 96KHz. 

    When AFD is enabled, 0x28[4:0] could change but since you are going to use custom mode 0x59[7:0] specifies the charge pump current.

    Note un-used bits are read only or you can read a register and modify the bits needed. Also please refer to data sheet for further details:

    Once you make these register changes please let me take a look at your register dump if you like.

    Regards,,nasser 

  • Nasser,


    Thanks!  The parameter I'm a little uncertain about is 0x59.  I wasn't sure whether to set it to the value at address 0x27 or 0x28.  I ended up setting it to the value at address 0x28 which was 0x05.  Not sure if that is right.  Also in your last post you said, "When AFD is enabled, 0x28[4:0] could change but since you are going to use custom mode 0x59[7:0] specifies the charge pump current."  I'm not sure what you meant by that.


    Here is my register dump for 192KHz:

    0x00 = 0x2c
    0x01 = 0x40
    0x02 = 0x80
    0x03 = 0xc0
    0x04 = 0x00
    0x05 = 0x2f
    0x06 = 0x08
    0x07 = 0x3e
    0x08 = 0x3e
    0x09 = 0x10
    0x0a = 0x7f
    0x0b = 0x00
    0x0c = 0x00
    0x0d = 0x00
    0x0e = 0x00
    0x0f = 0x00
    0x10 = 0x00
    0x11 = 0x34
    0x12 = 0x30
    0x13 = 0x30
    0x14 = 0x30
    0x15 = 0x02
    0x16 = 0x01
    0x17 = 0xd2
    0x18 = 0x02
    0x19 = 0x00
    0x1a = 0x00
    0x1b = 0x01
    0x1c = 0x10
    0x1d = 0x00
    0x1e = 0x00
    0x1f = 0x00
    0x20 = 0x1f
    0x21 = 0x08
    0x22 = 0x05
    0x23 = 0x06
    0x24 = 0x00
    0x25 = 0x01
    0x26 = 0x00
    0x27 = 0x1f
    0x28 = 0x05
    0x29 = 0x00
    0x2a = 0x08
    0x2b = 0x04
    0x2c = 0x65
    0x2d = 0x08
    0x2e = 0x08
    0x2f = 0x02
    0x30 = 0x0c
    0x31 = 0x08
    0x32 = 0x03
    0x33 = 0x05
    0x34 = 0x20
    0x35 = 0x08
    0x36 = 0x4b
    0x37 = 0x02
    0x38 = 0x00
    0x39 = 0x16
    0x3a = 0x49
    0x3b = 0x00
    0x3c = 0x01
    0x3d = 0x0a
    0x3e = 0x50
    0x3f = 0x04
    0x40 = 0x65
    0x41 = 0x00
    0x42 = 0x01
    0x43 = 0x08
    0x44 = 0x98
    0x45 = 0x04
    0x46 = 0x65
    0x47 = 0x00
    0x48 = 0x01
    0x49 = 0x01
    0x4a = 0x0b
    0x4b = 0x00
    0x4c = 0x00
    0x4d = 0x00
    0x4e = 0x00
    0x4f = 0x00
    0x50 = 0x00
    0x51 = 0x0b
    0x52 = 0x01
    0x53 = 0x0a
    0x54 = 0xf7
    0x55 = 0x00
    0x56 = 0x08
    0x57 = 0x04
    0x58 = 0x65
    0x59 = 0x05
    0x5a = 0x00
    0x5b = 0x01
    0x5c = 0x01
    0x5d = 0x88

  • Hi Brian,

    To lock LMH1983 runs in two stages: First it does fast lock by increasing charge pump current. In the next stage, once device is locked, it uses lower loop bandwidth in order to have as low jitter as possible. In the first stage or fast lock, register 0x27 is used and then once we are locked register 0x28 is used. I think using register 0x28 should be fine.

    Secondly, when AFD is enabled based on what video frame format is detected register 0x28 value may change.

    Regards,,nasser