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TLK3101 - Not Link established

Ryuji
Guru 20090 points

Hello,

Currently, the customer use 150MHz clock for TLK3101 , and the device can't establish the Link sometimes.
Are there any requirement for 150MHz clock for link establish?
Is this only, loss of signal detection requirement in the datasheet? (above 200mV in differential magnitude)

And if the device couldn't establish the link, should we process the device?
Should we change to the power down mode by enable pin and retry the initialization?

Best Regards,
Ryuji Asaka

  • 0
    TI__Genius 16150 points

    Hi Ryuji,

    1. Is the reference clock (GTX_CLK) of 150MHz into the timing requirements (Freq tol and jitter)?

    2. This device reports the condition of loss of signal through RX_DV/LOS, RX_ER and RDX all to  a high state (wether signal is above 200mV in differential magnite), are they getting errors and the LOS indicator is asserted?

    3.  The TLK3101 (PECL outputs) provides pre-emphasis to compensate AC loss, this preemphasis is controlled by PREM (5 or 20%).

    4. It is an option to retry the initialization, although, I do not know how much this scenario affects the performance of the application, if this is not relevant, it could be an option, but please, check another factors that I mentioned above.

    Best Regards,

    Luis Omar Morán Serna

    High Speed Interface

    SWAT Team

  • 0 in reply to Luis Omar Moran
    Guru 20090 points
    Hello Luis san,

    Thank you for the reply.
    I'm checking to the customer.

    Best Regards,
    Ryuji Asaka
  • 0 in reply to Luis Omar Moran
    Guru 20090 points
    Hello Luis san,

    Does GTX_CLK not have any problem before we initialize the device if a clock is stable?
    Are there any requirement for clock stability timing?

    For example, the clock must be stabled before reaching the min voltage of Vdd.
    If there is the documents such as this timing requirement, please share with us.

    We understood that there is no problem , if GTX_CLK is stable before Power ON reset.
    Is my understanding correct?

    Best Regards,
    Ryuji Asaka
  • 0 in reply to Ryuji
    TI__Genius 16150 points
    Hi Ryuji-san,

    You are right. there is no issues if this input GTX_CLK is stable before Power ON reset, as long as this clock signal is meeting the specs in data sheet.

    Best Regards,
    Luis Omar Morán Serna
    High Speed Interface
    SWAT Team
  • 0 in reply to Luis Omar Moran
    Guru 20090 points

    Hello Luis san,

    Is the effect of enable reset same with Power On reset ? 
    In the customer, GTX_CLK was changed by the switch of clock buffer after PoR.
    Thus, they would like to use , Enable for Reset.
    Is this no problem?

    Best Regards,
    Ryuji Asaka

  • 0 in reply to Ryuji
    TI__Genius 16150 points

    Hi Ryuji-san,

    Is not a problem. Basically, the ENABLE pin (Device enable) is used to placed the device in power-down mode when is held low. When is asserted high, firstly,the device goes into power-on reset before beginning normal operation.

    Best Regards,

    Luis