This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DS125RT410SQ related question

Other Parts Discussed in Thread: DPS-DONGLE-EVM, DS125DF410, DS125RT410

Hi,

We used DS125RT410SQ on our High speed line which will support OBSAI RP3-01 6.144G/3.072G/1.536G and CPRI 9.8304G/4.9152G/2.4576G.

The three channels of retime connect RP3-01/CPRI interface. Connection is as below:

ASIC TX->Retime Ch0 RX->Retime Ch0 TX->(loopback)->ASIC RX

ASIC TX->Retime Ch1 RX->Retime Ch1 TX->(loopback)->ASIC RX

ASIC TX->Retime Ch2 RX->Retime Ch2 TX->(loopback)->ASIC RX

I made a common configuration to configure the retime registers as below:

So far I test the all the RP3-01 link rate, there is no abnormal found with this configuration.

But when I test CPRI interface in 4.9125G, I found there are BER on some links when link startup sometimes, not always.

It means when the link start up , if there is BER then all the link will have BER, but when the link start up, if there is no BER, then it will not have BER.

I think it may related with Retime CTLE and CDR, I have some questions about this:

Q1: For the CPRI 4.9125G mode, I configure the VCO frequency as 9.8304 and divide ratio is 1,2,4,8. The divide ratio will automatically use 2, right? and the CTLE boost value will use the adaptive value, right?

Q2: When the divide ratio is 4 or 8, the CTLE boost setting will use the value from 0x3a, right? what the default value of 0x3a?

I found if I didn't change this value to low value(0x00), when I run low speed signal, the re-time will not output signal even the input signal is good

Q3: I see the register 0x13 bit2 set 1 can configure the CTLE to be a limiting mode, when will this be used? what's the difference with normal mode?

Q4 Is there any requirement for the input signal to the retime CDR? In other words, how can I verify the adaptive CTLE value is good enough which can boost the signal meet the CDR input requirement.

Q5: When is choose VCO frequency as 9.8304G, it calculated NPPM is 12582.912, it is not integer, how can I change it to hexadecimal value as your datasheet describe?

##############################

#Retimer1 Ch1 Configuration

##############################

< 0xff 0x05>

#reset_retimer_ch

<0x00 0x0c>

#Configuring Ret3 Ch1 VC0

<0x2f 0x64> #enable divider for 1, 2, 4, 8; set bit 1 to 0

<0x36 0x31> #enable ref-mode-3

<0x3a, 0x00>

< 0x60 0x70>

< 0x61 0xbd>

< 0x62 0x26>

< 0x63 0xb1>

< 0x64 0xff>

# Configuring Ret3 Ch1 Serdes TX Optimal Settings

<0x2d 0x80> #600mV

<0x15 0x11> #-2dB

# Reset CDR

< 0x0a 0x1c>

< 0x0a 0x10>

 

 

##############################

#Retimer1 Ch2 Configuration

##############################

< 0xff 0x06>

#reset_retimer_ch

<0x00 0x0c>

#Configuring Ret3 Ch1 VC0

<0x2f 0x64> #enable divider for 1, 2, 4, 8; set bit 1 to 0

<0x36 0x31> #enable ref-mode-3

<0x3a, 0x00>

< 0x60 0x70>

< 0x61 0xbd>

< 0x62 0x26>

< 0x63 0xb1>

< 0x64 0xff>

# Configuring Ret3 Ch1 Serdes TX Optimal Settings

<0x2d 0x80> #600mV

<0x15 0x11> #-2dB

# Reset CDR

< 0x0a 0x1c>

< 0x0a 0x10>

##############################

#Retimer1 Ch2 Configuration

##############################

< 0xff 0x07>

#reset_retimer_ch

<0x00 0x0c>

#Configuring Ret3 Ch1 VC0

<0x2f 0x64> #enable divider for 1, 2, 4, 8; set bit 1 to 0

<0x36 0x31> #enable ref-mode-3

<0x3a, 0x00>

< 0x60 0x70>

< 0x61 0xbd>

< 0x62 0x26>

< 0x63 0xb1>

< 0x64 0xff>

# Configuring Ret3 Ch1 Serdes TX Optimal Settings

<0x2d 0x80> #600mV

<0x15 0x11> #-2dB

# Reset CDR

< 0x0a 0x1c>

< 0x0a 0x10>

  • Hi,

    Q1: For the CPRI 4.9125G mode, I configure the VCO frequency as 9.8304 and divide ratio is 1,2,4,8. The divide ratio will automatically use 2, right? and the CTLE boost value will use the adaptive value, right?

    The device should automatically chose it divider setting based on the input data rate. And the CTLE will automatically go through an adaptation process to converge on the optimal boost value.

    Q2: When the divide ratio is 4 or 8, the CTLE boost setting will use the value from 0x3a, right? what the default value of 0x3a?

    The default value for 0x3A is 0xA5, which is a very high boost setting.

    I found if I didn't change this value to low value(0x00), when I run low speed signal, the re-time will not output signal even the input signal is good
    At low data rate, the insertion loss for your channel may be very small, and thus a high-boost setting could actually cause a problem. So setting 0x3A to 0x00 would be better for that condition.

    Q3: I see the register 0x13 bit2 set 1 can configure the CTLE to be a limiting mode, when will this be used? what's the difference with normal mode?

    When in limiting mode, the CTLE final stage output will be a larger amplitude that is more or less constant as a function of input amplitude. I don't usually recommend for limiting mode to be used for typical applications. Limiting mode could help for the scenario where the input signal to the retimer is over-equalized

    Q4 Is there any requirement for the input signal to the retime CDR? In other words, how can I verify the adaptive CTLE value is good enough which can boost the signal meet the CDR input requirement.


    I'm not too familiar with CPRI, but the interface standard would specify the input jitter tolerance for the retimer. The input signal should meet the jitter specs per the standard.Addiitonally, insertion loss for the channel should be within range than can be compensated by the equalizer. 

    Do you know the TX amplitude and de-emphasis settings being used for the testing? Perhaps the Tx input signal settings being used are not optimal.

    Q5: When is choose VCO frequency as 9.8304G, it calculated NPPM is 12582.912, it is not integer, how can I change it to hexadecimal value as your datasheet describe

    You can take advantage of our SigCon Architect GUI to do the manual mode settings calculation for you. For 9.8304G VCO frequency, you would load 0xB1 to channel registers 0x61 and 0x63, and 0x27 to channel registers 0x60 and 0x62

    SigCon Architect can be downlaoded via TI.com,

    www.ti.com/.../sigconarchitect

    Regards,

    Rodrigo Natal

  • Hi

    Thank you.

    >>I'm not too familiar with CPRI, but the interface standard would specify the input jitter tolerance for the retimer. The input signal should meet the jitter specs per the standard.Addiitonally, insertion loss for the channel should be within range than can be compensated by the equalizer. 

    Do you know the TX amplitude and de-emphasis settings being used for the testing? Perhaps the Tx input signal settings being used are not optimal.

    I need the input requirement of retime(at the input pin or one die eye requirement), then I can adjust my ASIC TX sederds outpur amplitude and de-emphasis settings to meet the retime specification.

    Without the requirement , I can't judge whether the input to the retime is good enough or not.

    Which register can I check whether the retime is working correctly, I mean the retime is not false lock or loss lock with the input signal.

    I try to read the 0x01 register bit4 and bit0, sometimes it is always 0x11 even the link is no BER found!

    sequence is like that:

    <0xff 0x04>  0x05, 0x06, 0x07select channel

    then read the 0x01 value.

     

    And how does the CTLE adaptive function and CDR works, if at the beginning, the output signal of the ASIC is not good, but after 10~50us, the signal become good, will this be a issue to retime lock to the input signal?

    Is the CTLE one time work, just adaptive its setting for the beginning of the input signal?

    How can reset the retime, to let it re-check the input signal? I used to write register 0x00 to value 0x0f for  each channel.

    sequence is like that:

    <0xff 0x04> 0x05, 0x06, 0x07select channel

    <0x00 0x0f> write 0x0f to 0x00

     

    BR,

    -Erick

     

     

     

  • Hi,

     need the input requirement of retime(at the input pin or one die eye requirement), then I can adjust my ASIC TX sederds outpur amplitude and de-emphasis settings to meet the retime specification. Without the requirement , I can't judge whether the input to the retime is good enough or not.

    I disagree. We do have capability at the retimer level to evlauate signal quality. Specifically the retimer has Rx eye monitor functionality.

     

    Which register can I check whether the retime is working correctly, I mean the retime is not false lock or loss lock with the input signal.

    You can read channel registers 0x27 and 0x28 to obtain real time reading of the horizontal eye opening and the vertical eye opening where

    Heo (in UI) = reg 0x27 decimal value / 64

    VEO (mV) = reg 0x28 decimal value * 3.125

     

    I try to read the 0x01 register bit4 and bit0, sometimes it is always 0x11 even the link is no BER found!

    sequence is like that:

    <0xff 0x04>  0x05, 0x06, 0x07select channel

    then read the 0x01 value.

    Please instead use the CDR lock status bit, channel register 0x02 bit 4

    And how does the CTLE adaptive function and CDR works, if at the beginning, the output signal of the ASIC is not good, but after 10~50us, the signal become good, will this be a issue to retime lock to the input signal?

    No that should not be an issue

    Is the CTLE one time work, just adaptive its setting for the beginning of the input signal?

    The CTLE adapts once when valid input signal is present. It will then not re-adapt unless the retimer is reset, or there is a significant change in the input signal (e.g. turn off then turn on.)

    How can reset the retime, to let it re-check the input signal?

    After selecting the desired channel via global register 0xFF you can put the retimer in reset by setting channel register 0x0A[3:2] ='11'. You can then release the reset by setting those two bits back to 0's.

     

    Cordially,

    Rodrigo Natal

  • >>I disagree. We do have capability at the retimer level to evlauate signal quality. Specifically the retimer has Rx eye monitor functionality.

    >>You can read channel registers 0x27 and 0x28 to obtain real time reading of the horizontal eye opening and the vertical eye opening where

    >>Heo (in UI) = reg 0x27 decimal value / 64

    >>VEO (mV) = reg 0x28 decimal value * 3.125

    I can read out this value and also I am applying for TI DPS-DONGLE-EVM, maybe I can catch out the eye diagram by GUI.

    But my questions is even I catch out that eye diagram by GUI, see its eye high and eye width, how do I know it is OK or not?

    In other words, I plan to optimize our ASIC TX serdes parameter(Amp, De-emphasis) to retime input, what's your opinion about how to optimize the retime input to let link work robustly. 

     

    >>Please instead use the CDR lock status bit, channel register 0x02 bit 4

    What is the difference of channel register 0x01 bit 4 and bit0? I see it is also indicate the CDR Lock/SIG_DET loss status. 

     

    >>After selecting the desired channel via global register 0xFF you can put the retimer in reset by setting channel register 0x0A[3:2] ='11'. You can then release the reset by setting those two bits back to 0's.

    I see these bit is to reset the CDR, will it also reset the CTLE?

    I also see channel register 0x00 can reset all the register to default value, does it will reset the CDR and CTLE?

    I am using 0x00 to reset channel at the every beginning  of retime configuration and link rate changing, is it necessary ?

    Sequence:

    Select Retime Ch

    Set 0X00 to 0X0F

     

    Best regards,

    -Erick

  •  

    Hi Erick, see below,

    I can read out this value and also I am applying for TI DPS-DONGLE-EVM, maybe I can catch out the eye diagram by GUI. But my questions is even I catch out that eye diagram by GUI, see its eye high and eye width, how do I know it is OK or not? In other words, I plan to optimize our ASIC TX serdes parameter(Amp, De-emphasis) to retime input, what's your opinion about how to optimize the retime input to let link work robustly.


    Ultimately the best indicator of link performance is bit error rate (BER). Unfortunately the DS125DF410 does not have PRBS checker function, but you may use a BERT or some PHY/retimer with PRBS checker function to validate with BER the Tx optimization chosen by looking at eye opening.

    What is the difference of channel register 0x01 bit 4 and bit0? I see it is also indicate the CDR Lock/SIG_DET loss status. 


    Channel register 1 has interrupt bits, not status bits. An interupt bit becomes asserted upon the event condition (e.g. loss of signal) but the bit is cleared upon a host read operation.

    I see these bit is to reset the CDR, will it also reset the CTLE?

    Yes.

    I also see channel register 0x00 can reset all the register to default value, does it will reset the CDR and CTLE?

    It may not. Rely on the CDR reset via channel register 0x0A.

    I am using 0x00 to reset channel at the every beginning  of retime configuration and link rate changing, is it necessary ?

    Not necessary, but it doesn't hurt. The reset function basically returns the channel registers to their default values.

  • Hi,

    I am trying to use TI DSP-dongle-EVM and GUI to catch the retime RX side internal eye-diagram.

    We are using DS125RT410 retime in project, I don't see any profile for DS125RT410, so I choose DS125DF410 instead.

     But I can't see the eye-diagram when I choose 'single capture' or 'continuous capture'.

    Do you know the causes? 

    I am using latest EVM GUI 2.0.07.

    BR,

    -Erick

  • Hi Yongjia,

    We do not have a profile for the DS125RT410, but you can use the DS125DF410 profile and ignore the DFE tap weights section of the High Level Page.

    I have known the GUI to malfunction sometimes when it is stuck in an unknown state during an eye capture. Have you tried closing and then restarting SigCon Architect, then taking an eye capture? This usually helps to reset the eye capture utility so that it displays appropriately while not changing any of the settings you already have in the DS125RT410.

    Thanks,

    Michael

  • Hi Michael,

    Thanks for your support.

    Yes, I have tried this, it was the same phenomenon.

    BR,

    -Erick

  • Hi Erick. It does appear that there is some inconsistency with EOM capture operation with latest SigCon Architect GUI Installer revision for some of our retimer part number profiles. We are looking into it, and will be addressing issues as promptly as possible.

    Cordially,

    Rodrigo Natal

    DPS Application Engineer

  • Hi,

    Any update?

    BR,

    -Erick

  • Hi Erick,

    We are still working on this issue. Sorry for the delay.

    Michael

  • Hi Erick,

    We recently created a fix for this issue, but we are still validating the updated profile. We can send this profile to you to update and check to see if the profile works with your setup. Can you please proceed an e-mail address that I can send the profile to?

    Thanks,

    Michael
  • Hi,
    My e-mail address is yongjia.cai@nokia.com

    BR,
    -Erick
  • Hi,

    Have you already sent it?

    I haven't received it yet.

    BR,

    -Erick

  • Hi Yongjia,

    I sent it last Friday (5/27) at 11:36 AM Pacific Time. Please let me know if you cannot locate it, and I will send it again.

    Regards,

    Michael
  • Hi,

    I don't find it in my mail-box, is it big size? maybe it was blocked.

    Could you try to send it again to yongjia.cai@nokia.com, and cc to my private mail address: caiyongjia07@126.com

    BR,

    -Erick

  • Hi Erick,

    I just sent you the profile again as requested. Please check your inboxes.

    Regards,

    Michael
  • Hi,

    I download it and install it.

    But it doesn't work on my side.

    My EVM GUI Version is 2.0.0.6

    BR,

    -Erick

  • Hi Erick,

    Something does not seem right. From your screenshot, I am wondering if the GUI profile actually was updated correctly in your version of SigCon Architect. I recommend uninstalling SigCon Architect first, using the latest one on TI.com (V2.0.0.8, though the only updates from V2.0.0.6 are aesthetic and not functional in nature), then install the DS125DF410 GUI profile I gave you.

    I double-checked the DS125DF410 GUI profile in our lab and we are seeing the eye monitor produce an eye without issue:

    Thanks,

    Michael

  • Hi,

    I download latest 2.0.0.8 version, uninstall the old one, reboot my pc, install latest one, then install the profile you send me.

    The issue is same.

    and my another colleague also try it, same with me.

    please check the profile you send me is correct or not.

    If you want resent me the profile, please be aware of my e-mail address is yongjia.cai@nokia.com and cc to my private e-mail caiyongjia07@126.com.

    Last time, I found you mistook my e-mail as yonjia.cai@nokia.com.

    And I have a question, from your screenshot, the eye-diagram resolution or accuracy is so low?

    BR,

    -Erick

  • Hi Erick,

    I believe Rodrigo has already sent you the updated DS125DF410 SigCon Architect GUI profile. Please let us know if it is working, and also please verify that you are seeing "Profile Version: 1.0.1.8" in the bottom right of the Configuration Page so that we know you are using the same profile version that we are.

    To answer your question in the previous post, the eye diagram that is shown is only a 64x64 representation of the eye as measured internally by the retimer. Therefore, the image will look quite pixelated, but it will still give you a good idea about the eye quality before the CDR so that you can determine whether the input EQ/DFE is sufficient.

    Regards,

    Michael
  • Hi,

    Yes, i received the profile, but the issue still at my side.

    I have no idea yet why it worked on your side but not work at my side.

    My environment is as below:

    EVM GUI:2.0.0.8

    Profile: 1.0.1.8

  • Hi. We are honestly scratching our heads a bit trying to figure out what the problem is, as we do not see this issue on our side. At this point my suggestion would be having a WebEx conference call, where perhaps you can share your desktop and show us exactly what you are doing. Let me know if that sounds like a reasonable idea.

    Cordially,

    Rodrigo Natal

    DPS Applications Engineer

  • Hi,

    I just installed the environment and select the device address, then start to capture the eye-diagram with the tool without any other configuration.

    I check the datasheet, it need to enable eye-monitor function with some registers, do I need also do that?

    For the con-call, I have free time this afternoon, please send me a e-mail to check whether I am free.

    BR,

    -Erick

  • If you are using the EOM tab on SigCon Architect, you should not need to manually execute the write operaitons for configuring retimer to eye capture mode. The GUI should do it for you. I will reply soon related to conference call timing.