Hi,
We used DS125RT410SQ on our High speed line which will support OBSAI RP3-01 6.144G/3.072G/1.536G and CPRI 9.8304G/4.9152G/2.4576G.
The three channels of retime connect RP3-01/CPRI interface. Connection is as below:
ASIC TX->Retime Ch0 RX->Retime Ch0 TX->(loopback)->ASIC RX
ASIC TX->Retime Ch1 RX->Retime Ch1 TX->(loopback)->ASIC RX
ASIC TX->Retime Ch2 RX->Retime Ch2 TX->(loopback)->ASIC RX
I made a common configuration to configure the retime registers as below:
So far I test the all the RP3-01 link rate, there is no abnormal found with this configuration.
But when I test CPRI interface in 4.9125G, I found there are BER on some links when link startup sometimes, not always.
It means when the link start up , if there is BER then all the link will have BER, but when the link start up, if there is no BER, then it will not have BER.
I think it may related with Retime CTLE and CDR, I have some questions about this:
Q1: For the CPRI 4.9125G mode, I configure the VCO frequency as 9.8304 and divide ratio is 1,2,4,8. The divide ratio will automatically use 2, right? and the CTLE boost value will use the adaptive value, right?
Q2: When the divide ratio is 4 or 8, the CTLE boost setting will use the value from 0x3a, right? what the default value of 0x3a?
I found if I didn't change this value to low value(0x00), when I run low speed signal, the re-time will not output signal even the input signal is good
Q3: I see the register 0x13 bit2 set 1 can configure the CTLE to be a limiting mode, when will this be used? what's the difference with normal mode?
Q4 Is there any requirement for the input signal to the retime CDR? In other words, how can I verify the adaptive CTLE value is good enough which can boost the signal meet the CDR input requirement.
Q5: When is choose VCO frequency as 9.8304G, it calculated NPPM is 12582.912, it is not integer, how can I change it to hexadecimal value as your datasheet describe?
##############################
#Retimer1 Ch1 Configuration
##############################
< 0xff 0x05>
#reset_retimer_ch
<0x00 0x0c>
#Configuring Ret3 Ch1 VC0
<0x2f 0x64> #enable divider for 1, 2, 4, 8; set bit 1 to 0
<0x36 0x31> #enable ref-mode-3
<0x3a, 0x00>
< 0x60 0x70>
< 0x61 0xbd>
< 0x62 0x26>
< 0x63 0xb1>
< 0x64 0xff>
# Configuring Ret3 Ch1 Serdes TX Optimal Settings
<0x2d 0x80> #600mV
<0x15 0x11> #-2dB
# Reset CDR
< 0x0a 0x1c>
< 0x0a 0x10>
##############################
#Retimer1 Ch2 Configuration
##############################
< 0xff 0x06>
#reset_retimer_ch
<0x00 0x0c>
#Configuring Ret3 Ch1 VC0
<0x2f 0x64> #enable divider for 1, 2, 4, 8; set bit 1 to 0
<0x36 0x31> #enable ref-mode-3
<0x3a, 0x00>
< 0x60 0x70>
< 0x61 0xbd>
< 0x62 0x26>
< 0x63 0xb1>
< 0x64 0xff>
# Configuring Ret3 Ch1 Serdes TX Optimal Settings
<0x2d 0x80> #600mV
<0x15 0x11> #-2dB
# Reset CDR
< 0x0a 0x1c>
< 0x0a 0x10>
##############################
#Retimer1 Ch2 Configuration
##############################
< 0xff 0x07>
#reset_retimer_ch
<0x00 0x0c>
#Configuring Ret3 Ch1 VC0
<0x2f 0x64> #enable divider for 1, 2, 4, 8; set bit 1 to 0
<0x36 0x31> #enable ref-mode-3
<0x3a, 0x00>
< 0x60 0x70>
< 0x61 0xbd>
< 0x62 0x26>
< 0x63 0xb1>
< 0x64 0xff>
# Configuring Ret3 Ch1 Serdes TX Optimal Settings
<0x2d 0x80> #600mV
<0x15 0x11> #-2dB
# Reset CDR
< 0x0a 0x1c>
< 0x0a 0x10>