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SDI Interface-SDI cable equalizer output jitter

Madhu Sharma
Expert 2915 points
Other Parts Discussed in Thread: LMH0344, LMH0346, LMH0366, LMH0303
Hi,
 
Whether the total output jitter of SDI cable equalizer with part number LMH0344 is within the limits specified by SMPTE 424 standards?
 
Thanks & Regards
Madhu Sharma K
  • 0
    TI__Guru* 88895 points

    Hi Madhu,

    Please let me know what SMPTE spec you are referring to. As far as i know, SMPTE does not specify output jitter for the SDI cable equalizer.

    Regards,,nasser

  • 0 in reply to Nasser Mohammadi
    Expert 2915 points
    Hi,

    In my design, I'm interfacing the equalizer with an FPGA. The FPGA vendor mentioned that FPGA receivers are characterized to meet the RX jitter tolerance as per the SDI spec. So I want to clarify below points:

    1) In LMH0344 datasheet, in page 7, jitter is mentioned for various cable lengths. Whether this indicates the maximum total jitter at the output for those cable lengths?
    2) Is there any possibility of output jitter going beyond the specified maximum limit ( such as when input itself has random jitter etc.)?

    Thanks & Regards
    Madhu Sharma K
  • 0 in reply to Madhu Sharma
    TI__Guru* 88895 points

    Hi Madhu,

    SMPTE Specifies jitter - in the form of timing and aliment jitter - at the output of the transmitter. However, i am not aware of a jitter spec at the output of the equalizer. SMPTE specifies parameters on the 75 ohm SDI side but not on the 100 ohm differential side. Having said this, please below note responses to your questions:

    1). Yes these are maximum total jitter(there is no filter to limit the jitter).

    2). Under the condition specified in the data sheet, this is the maximum jitter. However, if conditions noted in the data sheet are violated - for example the source transmitter has high jitter or longer cable length are used - then there maybe higher output jitter. I say maybe since this condition has not been characterized or evaluated.

    3). Could you please send us a block diagram of your project so we can get a good overview of your application? This would enable us to better answer your questions.

    Regards,,nasser

  • 0 in reply to Nasser Mohammadi
    Expert 2915 points

    Hi,

    Please find the SDI receiver block diagram below. Since the cable length will be more and there is a possibility of jitter, I have included a reclocker between FPGA and Equalizer. Please let me know whether the reclocker position ( between equalizer and fpga) is proper for eliminating jitter. Also please let me know if there is any other reclocker for SDI with better characteristics.

     

    Regards

    Madhu Sharma 

  • 0 in reply to Madhu Sharma
    TI__Mastermind 29635 points
    Hi Madhu,

    The positioning of the LMH0346 looks appropriate.

    Typically, the reclocker is placed in one of two locations, and it looks like your implementation uses Choice (1):

    1. After the Cable EQ device and before the FPGA or Cable Driver
    2. Before a Cable Driver device and after the FPGA or Cable EQ

    In addition to the LMH0346, you may also want to consider the LMH0366, which features lower power operation than the LMH0346 as well as an internal eye opening monitor (EOM) for debugging purposes.

    Thanks,

    Michael
  • 0 in reply to Michael Lu (Santa Clara)
    Expert 2915 points

    Hi Michael,

    The second case you mentioned: 2. Before a Cable Driver device and after the FPGA or Cable EQ

     

    What is the advantage of connecting th Reclocker between Cable driver and FPGA??

     

    Regards

    Madhu

  • 0 in reply to Madhu Sharma
    TI__Mastermind 29635 points
    Hi Madhu,

    If there is long trace between FPGA and Cable Driver, or if there is noise introduced from the FPGA to the cable driver, there may be benefit in using the reclocker to improve the signal quality before the signal is received by the cable driver.

    Can you share the application you are looking to design these parts for?

    Regards,

    Michael
  • 0 in reply to Michael Lu (Santa Clara)
    Expert 2915 points

    Hi Michael,

    In my application, the SDI camera will be far away from the board where equalizer is present. And, the FPGA will be very near to SDI driver. So I'm using reclocker only between equalizer and the FPGA. 

    For the reclocker LMH0346MH/NOPB,

    1)If the second output pins are not used, how to connect SCO/SDO2, its inverse signal and SCO_EN pins?


    2) Any design guidelines ( such as decoupling, layout recommendation etc) available for this device?

    3) Whether both VCCO and VCC can be connected to single 3.3V supply?

    Regards

    Madhu 

  • 0 in reply to Madhu Sharma
    TI__Mastermind 29635 points
    Hi Madhu,

    1. If the secondary output is unused, I recommend that you terminate the unused SDO2 outputs (both true and complement) with two 50-ohm resistors and a center tap capacitor to GND. You can leave SCO_EN disconnected, since it has an internal pull-down.

    2. We do not have any design guidelines yet for this specific device. However, feel free to use the 100-ohm side and power supply recommendations of the LMH0303 (Section 9, 10.1) as a reference.

    3. Yes, these can be connected to the same supply. I recommend using a 0-ohm or ferrite bead option to allow you to separate the two supplies if necessary.

    Thanks,

    Michael