Dear all:
We are designing a Display Port cable with using DS125DF410 chip, the cable length is (5-15)m/28AWG,and the lost is (10-34)db for 2.7Ghz. The Display Port work frequency is 1.62Ghz or 2.7Ghz. For example, configure mode2 or mode3(adaptive),but it was unlock at all. it was no image at any time. I thought that the CDR lock time is very slow when DP is traning. So I setup at mode 0, and then setup CTLE(0x03 0x3a 0x40) for manual and setup VCO frequency, I thought the CDR lock time is fast. This chip can output singal and locking(0x02=0xdc), but somting have unstable or boost is slow. Finally I setup raw data, it alway can be output normal signal and display is OK at any timing. do you have any suggestion about the CDR lock to give me or do you have any applications for the Display Port?
The manually register was setup below
//mode 0 //manual mode
{0x36,0x31}, //with a 25Mhz reference clock,reference clock mode[5:4],field=3[1:0]
{0x2f,0x66}, //{0x2f,0x62}, //Divider ratios 8/or 4/ or 2/or 1/,10.8Ghz/4=2.7Ghz,false lock detector is enable[1]=0
{0x60,0xcd}, //{0x60,0x00}, //PPM count,group 0, divider ratio 8, 10.8Ghzx1280=13824(0x3600)
{0x61,0xc0}, //{0x61,0xb0}, //PPM count,group 0, divider ratio 8, bit7=1(manual load)
{0x62,0x00}, //PPM count,group 1,divider ratio 8, 12.96Ghzx1280=16589(0x40CD)
{0x63,0xb0}, //PPM count,group 1,divider ratio 8, bit7=1(manual load)
{0x64,0xff}, //PPM count tolerance,(1x0.000001xNtol)/Nppm=TOLppm,=1085
{0x31,0x00}, //mode0,adapt CTLE until lock,then DFE, then EQ until optimal
{0x1e,0x29}, //retimer data
{0x3a,0xc5}, //EQ
{0x03,0xc5},
{0x40,0xc5},
best regard!
Bob Yang