REFCLK to RCLK delay time of DS92LV18

Hi Satoshi-san,

There is no specific parameter that specifies a min/typ/max for the delay time from REFCLK to RCLK.

However, since the REFCLK is simply just a reference to help the deserializer PLL achieve lock, I think the more critical parameter here may be the delay from the time the SYNC patterns arrive to the time lock is achieved and both ROUT[0:17] data and RCLK clock output become valid. This parameter is specified by tDSR2 (p. 5) in datasheet.

Thanks,

Michael

Satoshi,

For the DS92LV18 deserializer there is no required phase relationship between the REFCLK and RCLK.  The REFCLK is only required to be within 5% of the incoming data-rate recovered clock frequency to ensure the LV18 correctly deserializes the input data.

Datasheet propagation delay specifications assume a valid REFCLK input is present prior to the DS92LV18 beginning lock acquisition.

Regards,

Lee