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DS90UB914 VSYNC,HSYNC,DATA and PCLK no output

Hi Team,

The customer is using DS90UB913 and DS90UB914.  DS90UB913 can receive the signal of VSYNC,HSYNC,DATA and PCLK pins when the external crystal is connected to DS90UB913 . The external crystal is 48MHZ.

For DS90UB914, the customer uses BIST Self-Test, there is a 12MHZ output signal for the VSYNC pin,HSYNC pin and DATA pin and a 24MHZ  output signal for

PCLK pin.  But there are  not any output signals for VSYNC,HSYNC,DATA and PCLK pins in application,not in BIST Self-Test.

Q1: What is the reason? How to solve the issue?

Q2: And the customer need to get the initial setting register for   DS90UB913 and  DS90UB914.

Q3:  If the customer uses the external crystal and PLCK is 36MHZ, how much is external crystal?

Thanks,

Best Regards,5516.TI914.pdf

  • Can anyone see my issues? The customer is waiting for my reply.
  • Hello Mickey,

    1. In BIST mode, the internal clock being used is relatively low (~ 12.5 MHz) and this would need to be changed for your customer's specific system use-case in 10-bit mode. You can evaluate BIST either with external oscillator/PCLK or with internal PCLK. In order to evaluate with external oscillator like that being used in customer system, the GPIO[1:0] on 914A must be set to 0 (see below table). I also provide the info for performing BIST with internally generated PCLK below:

    If the customer is using 48 MHz clock, then input PCLK should be 96 MHz going into 913A device. In this case, we should set internal BIST clock to ~ 100 MHz. This can be done by setting BIST register 0x24 = 0x03  to enable BIST mode through register (not device pin) with PCLK of ~ 100 MHz in 10-bit mode.

    2. No initial register settings are needed; all default registers are set accordingly for proper system operation upon power-up. The only thing in your customer's use-case that needs to be set is BIST internal clk as shown above.

    3. Please see the 913A and 914A datasheets for this description and more information. This depends on the divider settings. For 48 MHZ clock which they are currently using, please see the below table. You should be able to deduce the proper values if instead of 48 MHz, they were using 36 MHz. Simply substitute 36 MHZ into the equations below:

    -Sean

  • Hello Mickey,

    Does the system LOCK properly without parity errors? This could be the reason they are not seeing the data displayed on 914A outputs.

    Regarding their issue with HSYNC, VSYNC, DATA, and PCLK not being displayed during application (not BIST), does PDB reset on 914A fix the issue? What about 913A PDB reset? Looking at 914A schematic, they only have 10k resistor pullup to PDB while it is recommended to have a larger RC time constant for proper operation (typically, 10k resistor + 10uF capacitor as shown in EVM User's Guide for 913A/914A).

    -Sean
  • Hi Sean,
    Thanks for your reply. I will query the customer, then I will reply you. E-mail: mickey-zhang@ti.com