I need clarification on an issue I am seeing with the I2C communication path using the DS90UB925 and DS90UB926 FPD chipset combination. In general, I am now at a point where I can read and write my I2C slave's memory with no errors but I am seeing something that I don't understand. My I2C master is paired with the 925 chipset and my remote device is communicating via the 926. When I attempt to read multiple bytes from the slave successively via the I2C interface I do the following with the master:
SEND: START BIT -> SLAVE ADDRESS (R/W BIT = 0) -> MEMORY ADDRESS (2 - bytes long) -> RE-START BIT -> SLAVE ADDRESS (R/W BIT = 1) -> CLOCK STREAM (continued groups of clocks to read out the memory bytes) -> NAK (for last read) -> STOP BIT
When I monitor the I2C bus between the 926 and I2C slave I see the start bit, slave address translated to the alias programmed in the FPD chipset (with R/W bit = 0), starting memory address, and the clock stream. The issue that is concerning me is that I see a re-start bit and a repeat of the translated slave address on this bus after every second byte is read. Is this how the FPD link I2C interface normally operates for a multiple byte read or did I configure my devices incorrectly? Once I modified the slave FPGA device to accept this repeated start and address I was able to read all of the data successfully but I am trying to understand the source of these signals as this is my first design using the FPD chipset. Any input is appreciated.