LMH1218 - SMBus, Maximum clock low period.

Hi Kawai-san,

When viewing both the SMBus and I2C interface characteristics, there is actually no max specified for tLOW, and these parameters in our datasheet either match or exceed the SMBus 2.0 specifications.

The reason for this is actually because of the situation your customer has asked. In the SMBus standard, it allows for the SMBus CLK to be held low and "stretched" between byte transfers on the bus, either by the slave or master. This extension is defined by TLOW:SEXT (slave clock-low extension) and TLOW:MEXT (master clock-low extension):

Therefore, if you are operating a full-speed slave and master, than the maximum clock low period may be 50 us, but due to the possibility of clock stretching by either slave or master, the clock line can be held longer than the 50 us you suggest, hence no maximum value in the datasheet.

Thanks,

Michael

Hi Kawai-san,

Yes, this is my understanding according to the SMBus timing specifications and LMH1218 behavior.

I believe there is still a maximum clock low limit, but this is defined by the maximum time limit is defined by the clock stretching limits for the master and slave as described in the SMBus timing specification.

Thanks,

Michael