ds90ub914a-q1 Parity Error Reset

Masaaki Sugiyama

Dear support team

0x03[1] bit is Parity Error Reset bit.
If we set "1" at 0x03[1] , are 0x1a and 0x1b registers clear("00")?

Best Regards

Masaaki Sugiyama

0 Sean Thornton1 over 7 years ago

Hello,

That is correct. Keep in mind that 0x03[1] is NOT self-clearing bit. It must be set back to 0 to accumulate/count possible errors.

-Sean

0 Masaaki Sugiyama over 7 years ago in reply to Sean Thornton1

Dear Sean-san

Thank you for your quick reply.

One more question.

0x1a and 0x1b registers become able to write in the datasheet.

0x1A	Parity Errors	7:0	Parity Error Byte 0	RW	0x00'h	Number of parity errors in the Forward channel during normal operation. Least significant Byte.
0x1B	Parity Errors	7:0	Parity Error Byte 1	RW	0x00'h	Number of parity errors in the Forward channel during normal operation. Most significant Byte.

But I tried to write 0x1a and 0x1b registers on EVM, I can not written.

Are these registeres read only?

Best Regards

Masaaki Sugiyama

0 Sean Thornton1 over 7 years ago in reply to Masaaki Sugiyama

Hello,

These registers are read only. RW is a typo. Thank you for catching this.

-Sean

0 Masaaki Sugiyama over 7 years ago in reply to Sean Thornton1

Dear Sean-san

Thank you for your kind support.

When you revise data sheet, please correct upper items, too.

Best Regards

Masaaki Sugiyama

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