SN75DPHY440SS: Device for skew/de-skew on MIPI DPHY

Hello Joey,
The DPHY440 is designed to provide a skew correction in a differential transmission circuit. A possible solution to insert skew would be by changing the trace length for signal or implementing delay-time compensation.
Regards

Hi Joel,

Can you explain the specs for common-mode interface & common-level variations (for HS Rx and Tx) for 50MHz-450MHz and 450MHz beyond?

The customer is trying to understand what this spec means.

Hello,

You can referer to the DPHY 1.1 spec for in-depth details on the HS Receiver/Transmitter AC Specifications

The High-Speed receiver will receive High-Speed data correctly while rejecting common-mode interference ∆VCMRX(HF) and ∆VCMRX(LF)

ΔVCMRX(HF) is the peak amplitude of a sine wave superimposed on the receiver inputs.
ΔVCMRX(LF) Voltage difference compared to the DC average common-mode potential.

The transmitter will send data such that the high frequency and low frequency common-mode voltage variations do not exceed ∆VCMTX(HF) and ∆VCMTX(LF).

Regards

Great, thanks Joel!

The datasheet lists the input failsafe leakage current under the conditions of ‘VCC = 0 V; VDD = 0 V; MIPI DPHY pulled up to 1.35 V’.

Do we have the leakage current onto the MIPI DPHY DSI lanes (DATA and CLK) when;

1. VCC=1.8V, VDD=1.2V AND RST is low
2. VCC=1.8V, VDD=1.2V AND RST is high

The customer is asking for this information for power sequencing concerns. They want to know what will happen if the IC is powered up first and if there would be leakage into the MIPI lanes.

Can you also confirm that I2C is not required to be connected and they can configure those pins using external resistors?

Hi Joel,

Do you have an update on this?

Thanks, Joey

Hello Joey,

The requirement under the condition you mentioned is stated in the "MIPI DPHY HS RECIEVER INTERFACE" under the Electrical characteristics section.

The DPHY440 ignores all activity on the DA[3:0]P/N and DACP/N pins while in reset mode.

The equalization level and the HS edge rate may be determined by the state of the EQ/SCL and ERC/SDA pin at the rising edge of RSTN. You will need to use the I2C interface to access the advanced EQ and edge control features.

Regards