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DS92LX2122: DS92LX211 and DS92LX2122 signal reliability and losing lock

Part Number: DS92LX2122
Other Parts Discussed in Thread: DS92LX2121,

Hi

We are using the DS92LX2121 / DS92LX2122 parts in our display application.  I can not seem to get these parts to be reliable, they lose lock or have intermittent I2C errors. I have spent considerable time with Power supply filtering and decoupling. Any time there is EMI interference the parts lose lock. This can range from switching on a desk lamp or a static discharge into a cubicle wall several feet away. The lock pin drops low for 1 -10uS.

Placing ferrite beads on the signal and power cables seems to have reduced the problems but not eliminate them. Losing lock can cause the I2C to error and or the LCD to glitch. We are using a custom cable with Power, Gnd, and a single 100ohm twisted pair.

Is there any sort of design support we can get to help figure this out?

  • Hi Darryl,

    Thanks for your post, and sorry for the slight delay.

    From your comments, it looks like you have already addressed the typical culprits for transmission issues.

    We have seen in the past that sometimes the communication is affected by issues with Back-Channel Communication (BCC), as one potential issue is that the SerDes chipset is not implementing optimal echo-cancellation. For general purpose cables, we have seen that setting Des Reg 0x27 = 0xE0 helps. Can you check if that may help in your case?

    Regards,

    Michael
  • Michael

    I have confirmed with our Firmware programmer that Register 0x27 = 0xE0.

    Are there any other registers that may assist with this? And is there any documentation to accompany them?
  • Hi Darryl,

     

    Thank you for confirming the register setting.

     

    To better assist you on this request, can you send the schematic and layout to us for review? There are couple of areas that may cause the lock issue.

     

    •           For obtaining optimal performance the system should use (page 33 on ds92lx2121.pdf)

    • Shielded Twisted Pair (STP) cable

    • 100Ω ± 10% differential impedance and 24 AWG (or lower AWG) cable

    • Low intra-pair skew (less than 0.1UI), impedance matched

    • Terminate unused conductors

    • Optimum settings for deserializer Register 0x27 (See Table 2)

    •           View CML signal quality after the EQ

    •           Review Power / ground layout and schematic to look for ways to improve performance during EMI events

     

    You can send the schematic and supporting documents to my email at dennis.wu@ti.com

     

    Regards,

    Dennis