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DS100KR401: High speed layout guidelines for the DS100KR401

Part Number: DS100KR401

              I am looking at the TI chip DS100KR401 and have a question about layout. Since these are 10G lines I would like to make them as neat and clean as possible. Shown below is the current layout that I have.....

 

 My concern is the exit from DS100KR401. As you can see, pins 45 through 39 are having to fan out to reach the decoupling caps that they are attached to. However, pins 38 and 37 also need to make it out to the AC coupling caps on the right. These are blocked by the power VIA on pin 36. Also, pins 35 through 28 are signals as well. I would have to move the ac coupling caps further away from the DS100KR401 in order to make wiring all the pins possible. I would also need to stagger vias to make things fit.

 

My question is, does TI have any recommendation on how to lay out this device to produce the best signal integrity? The above arrangement seems like it will wind up being messy. Can you see if anyone can comment on how to improve the wiring from a signal integrity standpoint?