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SN65DSI84: 1024x600 resolution problem

Charles Trepanier35
Prodigy 30 points
Part Number: SN65DSI84

Hi everyone,

I am working on a design based on this mipi-lvds bridge to drive either a 1280x800 10" lcd or a 1024x600 7" lcd. The video source is an Intel Atom x5-Z8350 cpu on an Upboard SBC. 

My problem is that the bridge works well when the 1280x800 resolution is selected in the BIOS but not with the 1024x600.

Hardware

  • Two DSI channels (DA0-DA1) and only LVDS channel A are used.
  • The DSI clock is not used since we couldn't enable it on the cpu.
  • An external refclock is provided by an oscillator of 25MHz (7" LCD) or 35MHz (10" LCD).

Configuration

  • Configuration has been generated with TI's DSI Tuner.
  • The DSI source is 24bbp.
  • The REFCLK_MULTIPLIER register is set at 2 to generate the 50MHz and 70MHz LVDS clock needed by the displays.
  • Panel inputs and DSI inputs have been verified using the LCD datasheets and the video BIOS settings.
  • Related registers are configured for either the 25MHz or 35MHz refclock.

Results

  • The 10" configuration is working on the 10" LCD and the 7" LCD (works with 7" LCD even if the LVDS clock is higher than specified in the display's datasheet).
  • The 7" configuration is not working; LVDS lanes Y1 and Y3 seem to be dc biased but have no activity on them.
  • Both the 50MHz and 70MHz LVDS clocks are generated successfully by the sn65dsi84.
  • When the refclk is provided by an externel frequency generator set to 50MHz and having REFCLK_MULTIPLIER set to 1, the LVDS clock looks fine but still nothing on Y1 and Y3.
  • If the test pattern is activated (register 0x3c) with the 7" configuration, the display is white with a black border. 

Both DSI tuner configurations are attached.

Any insight on what could be wrong and what should be further tested would be greatly appreciated.

Thank you,

Charles

6253.7_inches.config 
%CHIP2%PVCAHKSebo New Display Co%PMCANDS7G50PIPS-3.5%RPCA1024%RLCA600%PVCB%PMCB%RPCB%RLCB%LVCM0%HPWA20%HBPA140%HFPA160%HACA1024%HTOA1344%HPWB%HBPB%HFPB%HACB%HTOB0%VPWA3%VBPA20%VFPA12%VACA600%VTOA635%VPWB%VBPB%VFPB%VACB%VTOB0%PCKN51.2%LCKS1%RCKM25%MULT1%DCKA%DIVI3%LCKR50.0%FMTA1%DEPA0%HSPA1%VSPA1%BPPA1%FMTB1%DEPB0%HSPB1%VSPB1%BPPB0%PRDA1024x600%PRDBx%DSCM0%LREO1%LRCE1%LPCA0%BMCA1%SMCA1%LPCB0%BMCB0%SMCB0%DHPA112%DHBA40%DHFA168%DHAA1024%DHTA1344%DHPB%DHBB%DHFB%DHAB%DHTB%DVPA29%DVBA1%DVFA5%DVAA600%DVTA635%DVPB%DVBB%DVFB%DVAB%DVTB%DDRA51%NOLA1%VIMA2%LCRP%DDRB%NOLB0%VIMB0%RCRP
5504.10_inches.config 
%CHIP2%PVCAHKSebo New Display Co%PMCAYX101IA-01G%RPCA1280%RLCA800%PVCB%PMCB%RPCB%RLCB%LVCM0%HPWA80%HBPA0%HFPA40%HACA1280%HTOA1400%HPWB%HBPB%HFPB%HACB%HTOB0%VPWA10%VBPA3%VFPA10%VACA800%VTOA823%VPWB%VBPB%VFPB%VACB%VTOB0%PCKN71.1%LCKS1%RCKM35%MULT1%DCKA%DIVI3%LCKR70.0%FMTA1%DEPA0%HSPA1%VSPA1%BPPA1%FMTB1%DEPB0%HSPB1%VSPB1%BPPB0%PRDA1280x800%PRDBx%DSCM0%LREO1%LRCE1%LPCA0%BMCA1%SMCA1%LPCB0%BMCB0%SMCB0%DHPA32%DHBA48%DHFA80%DHAA1280%DHTA1440%DHPB%DHBB%DHFB%DHAB%DHTB0%DVPA10%DVBA3%DVFA10%DVAA800%DVTA823%DVPB%DVBB%DVFB%DVAB%DVTB%DDRA71%NOLA1%VIMA2%LCRP%DDRB%NOLB0%VIMB0%RCRP

  • 0
    TI__Mastermind 18655 points

    Hello Charles,

    Please, provide the 7" LCD datasheet and a register dump of the DSI84.

    In your description you mentioned the following:

    • The DSI clock is not used since we couldn't enable it on the cpu.

    Does it mean that you do not have any DSI Clock connected to the DSI84? Even when the external reference clock is selected as clock source of the external LVDS clock you will need to input a DSI clock since DPHY spec.

    The D-PHY provides a synchronous connection between Master and Slave. A practical PHY Configuration consists of a clock signal and one or more data signals.

    Regards

  • 0 in reply to Joel Jimenez0
    Prodigy 30 points

    Hi Joel,

    Thanks for the quick reply.

    I have attached the 7" display datasheet and the DSI84 CSR registers values we send through I2C.

    The DSI clock signal is indeed connected to the DSI84, but it has no activity on it, as we were not able to activate it yet. 

    I thought that the clocking could be embedded with the data lanes, but after further research I believe I was mistaken with the M-PHY specification, which has this capability.

    Thank you,

    Charles

    2352.NDS7G50PIPS2016-5-31.pdf

    8130.7inch_v2.txt 
    //=====================================================================
// Filename   : 7inch_v2.txt
//
//   (C) Copyright 2013 by Texas Instruments Incorporated.
//   All rights reserved.
//
//=====================================================================
0x09              0x00
0x0A              0x02
0x0B              0x00
0x0D              0x00
0x10              0x36
0x11              0x00
0x12              0x3d
0x13              0x00
0x18              0x78
0x19              0x00
0x1A              0x03
0x1B              0x00
0x20              0x00
0x21              0x04
0x22              0x00
0x23              0x00
0x24              0x00
0x25              0x00
0x26              0x00
0x27              0x00
0x28              0x20
0x29              0x00
0x2A              0x00
0x2B              0x00
0x2C              0x14
0x2D              0x00
0x2E              0x00
0x2F              0x00
0x30              0x03
0x31              0x00
0x32              0x00
0x33              0x00
0x34              0x8c
0x35              0x00
0x36              0x00
0x37              0x00
0x38              0x00
0x39              0x00
0x3A              0x00
0x3B              0x00
0x3C              0x00
0x3D              0x00
0x3E              0x00


The PLL_EN bit and SOFT_RESET bit are not set as they need to be set per the recommended sequence defined in the datasheet

  • 0 in reply to Charles Trepanier35
    Prodigy 30 points

    Just to follow up,

    We were able to solve our issues with the bridge.

    We thought the DSI clock was disabled, but upon further investigation and better measurements, we found out it was actually always active. We had to hack into the graphics driver to disable it and the enable it following the timings of the initialization sequence of the datasheet. Eventually this will all be done in the BIOS. 

    Now we have our display working as expected.

    Thanks,

    Charles