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Linux/SN65DSI84-Q1: Compatibility with samsung s5pv4418, diagnosing DSI input

Part Number: SN65DSI84-Q1
Other Parts Discussed in Thread: SN65DSI84

Tool/software: Linux

Hi

I have chip SN65DSI84-Q1 and attemp to use it with samsung s5p4418 SoC for single and dual channel displays.

1. My SoC have voltage 3.3 v, and chip SN65DSI84 have 1.x v (chip clock source is DSI input). Can this schema operate normally? What should we do on hardware level?

2. I can read register 0xE5 and it shows me these values (for different configurations): 0x7d, 0xfd, 0x71, but never 0x01. 

Is my first task to make register 0xE5 show me value 0x01 and there is no sense to attach display while E5 shows error?

My code for i2c configuration:

// 09
i2c_smbus_write_byte_data(dsi85_i2c_client, DSI85_SOFT_RESET, 0x01);
// 0D
i2c_smbus_write_byte_data(dsi85_i2c_client, DSI85_PLL_EN, 0x00);

msleep(10);

// 0A
i2c_smbus_write_byte_data(dsi85_i2c_client, DSI85_CORE_PLL, 0x05); // val
// 0B
i2c_smbus_write_byte_data(dsi85_i2c_client, DSI85_PLL_DIV, 0x28); // 0x00 ; Divide DSI_CLK by 3. 0x010

/* four DSI lanes with single channel*/
// 10
i2c_smbus_write_byte_data(dsi85_i2c_client, DSI85_DSI_CFG, 0x26); // 0x20
// 11
i2c_smbus_write_byte_data(dsi85_i2c_client, DSI85_DSI_EQ, 0x00); // 00

/* set DSI clock range */
// 12
i2c_smbus_write_byte_data(dsi85_i2c_client, DSI85_CHA_DSI_CLK_RNG, 0x54); // 5d
// 13
i2c_smbus_write_byte_data(dsi85_i2c_client, DSI85_CHB_DSI_CLK_RNG, 0x00);

/* set LVDS for single channel, 24 bit mode, HS/VS low, DE high */
// 18
i2c_smbus_write_byte_data(dsi85_i2c_client, DSI85_LVDS_MODE, 0x72); // 7f ; 60

/* set LVDS 200 Ohm termination and max differential swing voltage */
// 19
i2c_smbus_write_byte_data(dsi85_i2c_client, DSI85_LVDS_SIGN, 0x00);
// 1A
i2c_smbus_write_byte_data(dsi85_i2c_client, DSI85_LVDS_TERM, 0x03);
// 1B
i2c_smbus_write_byte_data(dsi85_i2c_client, DSI85_LVDS_CM_ADJUST, 0x00);

/* x resolution high/low for channel A */
// 20
i2c_smbus_write_byte_data(dsi85_i2c_client, DSI85_CHA_LINE_LEN_LO, 0x00);
// 21
i2c_smbus_write_byte_data(dsi85_i2c_client, DSI85_CHA_LINE_LEN_HI, 0x04);

/* x resolution high/low for channel B */
// 22
i2c_smbus_write_byte_data(dsi85_i2c_client, DSI85_CHB_LINE_LEN_LO, 0x00);
// 23
i2c_smbus_write_byte_data(dsi85_i2c_client, DSI85_CHB_LINE_LEN_HI, 0x00);

/* y resolution high/low for channel A */
// 24
i2c_smbus_write_byte_data(dsi85_i2c_client, DSI85_CHA_VERT_LINES_LO, 0x00);
// 25
i2c_smbus_write_byte_data(dsi85_i2c_client, DSI85_CHA_VERT_LINES_HI, 0x03);

/* y resolution high/low for channel B */
// 26
i2c_smbus_write_byte_data(dsi85_i2c_client, DSI85_CHB_VERT_LINES_LO, 0x00);
// 27
i2c_smbus_write_byte_data(dsi85_i2c_client, DSI85_CHB_VERT_LINES_HI, 0x00);

/* SYNC delay high/low for channel A */
// 28
i2c_smbus_write_byte_data(dsi85_i2c_client, DSI85_CHA_SYNC_DELAY_LO, 0x20);
// 29
i2c_smbus_write_byte_data(dsi85_i2c_client, DSI85_CHA_SYNC_DELAY_HI, 0x00);

/* SYNC delay high/low for channel B */
// 2A
i2c_smbus_write_byte_data(dsi85_i2c_client, DSI85_CHB_SYNC_DELAY_LO, 0x00);
// 2B
i2c_smbus_write_byte_data(dsi85_i2c_client, DSI85_CHB_SYNC_DELAY_HI, 0x00);

/* HSYNC width high/low for channel A */
// 2C
i2c_smbus_write_byte_data(dsi85_i2c_client, DSI85_CHA_HSYNC_WIDTH_LO, 0x80);
// 2D
i2c_smbus_write_byte_data(dsi85_i2c_client, DSI85_CHA_HSYNC_WIDTH_HI, 0x00);

/* HSYNC width high/low for channel B */
// 2E
i2c_smbus_write_byte_data(dsi85_i2c_client, DSI85_CHB_HSYNC_WIDTH_LO, 0x00);
// 2F
i2c_smbus_write_byte_data(dsi85_i2c_client, DSI85_CHB_HSYNC_WIDTH_HI, 0x00);

/* VSYNC width high/low for channel A */
// 30
i2c_smbus_write_byte_data(dsi85_i2c_client, DSI85_CHA_VSYNC_WIDTH_LO, 0x01);
// 31
i2c_smbus_write_byte_data(dsi85_i2c_client, DSI85_CHA_VSYNC_WIDTH_HI, 0x00);

/* VSYNC width high/low for channel B */
// 32
i2c_smbus_write_byte_data(dsi85_i2c_client, DSI85_CHB_VSYNC_WIDTH_LO, 0x00);
// 33
i2c_smbus_write_byte_data(dsi85_i2c_client, DSI85_CHB_VSYNC_WIDTH_HI, 0x00);

/* Horizontal BackPorch for channel A */
// 34
i2c_smbus_write_byte_data(dsi85_i2c_client, DSI85_CHA_HORZ_BACKPORCH, 0x28);

/* Horizontal BackPorch for channel B */
// 35
i2c_smbus_write_byte_data(dsi85_i2c_client, DSI85_CHB_HORZ_BACKPORCH, 0x00);

/* Vertical BackPorch for channel A */
// 36
i2c_smbus_write_byte_data(dsi85_i2c_client, DSI85_CHA_VERT_BACKPORCH, 0x09);

/* Vertical BackPorch for channel B */
// 37
i2c_smbus_write_byte_data(dsi85_i2c_client, DSI85_CHB_VERT_BACKPORCH, 0x00);

/* Horizontal FrontPorch for channel A */
// 38
i2c_smbus_write_byte_data(dsi85_i2c_client, DSI85_CHA_HORZ_FRONTPORCH, 0x28);

/* Horizontal FrontPorch for channel B */
// 39
i2c_smbus_write_byte_data(dsi85_i2c_client, DSI85_CHB_HORZ_FRONTPORCH, 0x00);

/* Vertical FrontPorch for channel A */
// 3A
i2c_smbus_write_byte_data(dsi85_i2c_client, DSI85_CHA_VERT_FRONTPORCH, 0x04);

/* Vertical FrontPorch for channel B */
// 3B
i2c_smbus_write_byte_data(dsi85_i2c_client, DSI85_CHB_VERT_FRONTPORCH, 0x00);

i2c_smbus_write_byte_data(dsi85_i2c_client, 0x3D, 0x00);
i2c_smbus_write_byte_data(dsi85_i2c_client, 0x3E, 0x00);

// 3C TEST PATTERN
i2c_smbus_write_byte_data(dsi85_i2c_client, 0x3C, 0x10);


/* Soft reset and enable PLL */
msleep(10);
i2c_smbus_write_byte_data(dsi85_i2c_client, DSI85_PLL_EN, 0x01);
msleep(10);
i2c_smbus_write_byte_data(dsi85_i2c_client, DSI85_SOFT_RESET, 0x01);

3. Using Tuner v2.0 I make values for configuration registers

0x09 0x00
0x0A 0x05
0x0B 0x28
0x0D 0x00
0x10 0x26
0x11 0x00
0x12 0x54
0x13 0x00
0x18 0x72
0x19 0x00
0x1A 0x03
0x1B 0x00
0x20 0x00
0x21 0x04
0x22 0x00
0x23 0x00
0x24 0x00
0x25 0x03
0x26 0x00
0x27 0x00
0x28 0x20
0x29 0x00
0x2A 0x00
0x2B 0x00
0x2C 0x80
0x2D 0x00
0x2E 0x00
0x2F 0x00
0x30 0x01
0x31 0x00
0x32 0x00
0x33 0x00
0x34 0x28
0x35 0x00
0x36 0x09
0x37 0x00
0x38 0x28
0x39 0x00
0x3A 0x04
0x3B 0x00
0x3C 0x10
0x3D 0x00
0x3E 0x00

This is my display (1024x768 single channel) with test pattern enabled. Is this picture shows correct test pattern image? What i will see if all things will be ok?

  • Hello Oleg,

    The DSI lane leves should be provided as per D-PHY spec. Refer to the Electrical Characteristics table to check the MIPI DSI INTERFACE parameters.

    Please, make sure you are performing the power-up sequence correctly as stated in the datasheet. Confirm sure you have the MIPI inputs driven to LP11(both P and N pairs of all MIPI DSI differential pairs to single ended high ~1.2V) prior to asserting EN pin.

    Regards
  • Hi,

    We're also using  SN65DSI84-Q1 with an NVIDIA TX2. Since the NVIDIA TX2 only has DSI outputs, we're using SN65DSI84-Q1 as the bridge.

    Initialization Sequence Description
    Init seq1                            After power is applied and stable, all DSI Input lanes including DSI CLK(DA x P/N, DB x P/N) MUST be driven to
                                              LP11 state.
    Init seq2                            Assert the EN pin
    Init seq3                            Wait for 1ms for the internal voltage regulator to stabilize
    Init seq4                            Initialize all CSR registers to their appropriate values based on the implementation (The SN65DSI84-Q1 is not
                                              functional until the CSR registers are initialized)
    Init seq5                             Start the DSI video stream
    Init seq6                             Set the PLL_EN bit(CSR 0x0D.0)
    Init seq7                             Wait for a minimum of 3 ms.
    Init seq8                             Set the SOFT_RESET bit (CSR 0x09.0)

    I uderstand seq 1,2 and 3. But appreciate if you can explain how seq 4,6 and 8 can be done.  How do we program the SN65DSI84-Q1 registers?

    Thank you.

  • Hello Nipuna Weeratunge,

    The internal register of the SN65DSI84-Q1 should be configured through its local I2C interface.

    Please take a look at figure 5. RESET and Initialization Timing Definition While VCC is High which describes the init sequence requirement. 

    Regards