What if the parallel data in is asynchronous for DS92LV8028? Does it matter if the clock edge is on the data edge every once in awhile? Metastability? What do I do about it when the LVDS is interfaced to an FPGA.
Hi Paul,
All 8 channels need to synchronous to one parallel clock. Figure 4 of datasheet shows data is strobing at rising edge of the TCLK. The serializer accepts data from the inputs DINn0 to DINn9. The serializer uses the rising edge of the TCLK input to latch incoming data. If the parallel data is asynchronous, we can’t guarantee the output data transfer.
The serializer is paired with another deserializer. The serial data stream includes a start bit and stop bit appended by the serializer, which frame the ten data bits. The start bit is always high and the stop bit is always low. The start and stop bits also function as clock bits embedded in the serial stream. See Figure 7. for more details. In the case of FPGA as deserilizer, the FPGA has ability to identify those clock bits embedded in the serial stream.
Let me know if you have additional questions.
Regards,
Dennis
