Other Parts Discussed in Thread: TFP401A
Dear support team
Our customer has an issue about AC timing.
Please see the following file.
Could you tell us the maximum setup time?
Best regards
M.Sugiyama
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Dear support team
Our customer has an issue about AC timing.
Please see the following file.
Could you tell us the maximum setup time?
Best regards
M.Sugiyama
Dear Elias-san
Thank you for your reply.
I understand that the lower the frequency the longer the set-up time.
In this case,is the maximum setup time 16.2ns?
(pixel clock cycle:18ns - hold time:1.8ns = 16.2ns)
Of course, I understand that you can not guarantee this value.
Best Regards
M.sugiyama
Dear Elias-san;
Thank you for your reply.
When ODK_ONV = "0", do the control signals and QE,QO change by rising edge only?
I want to confirm that the control signals and QE,QO hold the data value until next rising edge.
Best Regards,
M.sugiyama
Dear Elias-san;
I am sorry for my typo.
I want to confirm that when CLK_INV=0, the output signals change no falling ODCK edge only.
Is it correct or not correct?
Best Regards,
M.Sugiyama
Dear Elias-san;
Thank you for your reply.
I summarized my Q&A.
Our customer request are maximum output delay and minimum output delay.
Could you confirm the following file?
Best Regards,
M.Sugiyanma