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DS90UB949-Q1: [ URGENT ] Data rate and Clock Frequency

Kenichiro
Mastermind 9165 points
Part Number: DS90UB940-Q1

[ DS90UB940 ] [ URGENT ] Data rate and Clock Frequency

Hi,

Can you help my customer to use DS90UB925 and DS90UB940 as the connection below?


What my customer expect is to have output data with 192MHz clock (76.8MHz x 2.5).
However, the clock rate is 537.6MHz and it's bigger than actual data rate.
Is there any way to have data with 192MHz?


Thank you for your support in advance.
Regards,
Ken

  • 0
    TI__Genius 14015 points

    Hi Ken,

    It sounds like the 940 is configured for 2-lane CSI-2 output. In that mode, we expect the clock to be 7 times the PCLK. 

    In 4-lane CSI-2 mode, we expect the clock to be 3.5 times the PCLK - so 268.8MHz in this case. 

    Can you confirm that the 940 is in 2-lane mode by reading back 0x6A[5:4]? If that is set for 2-lane and you want 4-lane, you can either change the setting in register or check the MODE_SEL0 resistor divider.

    Thanks,
    Jason

  • 0 in reply to Jason Blackman
    Mastermind 9165 points
    Hi Jason,

    Thank you for your support!!
    You are right, my customer has configured DS90UB940-Q1 in 2-lane CSI output mode. That's means the mipi clock rate would be 7 times of PCLK.

    I also found that it seems that they have not set the 0x6B (CSICFG1) bits correctly. So I asked them to check as well.

    One confirmation, Jason.
    My customer use DS90UB925 and DS90UB940 to transmit RAW10. The DIN0 through DIN9 of DS90UB925 is used as input in conjnction with 76.8MHz PCLK (24bit mode). Also, DS90UB940 should be set to RAW10 mode with 2-lane CSI output.

    In this set-up, if output mipi clock is based on input PCLK (76.8MHz), it seems the output data rate is higher than transmitted data rate, because just 10bits ouf of 24bit are used. I guess the equal data rate for RAW10 is 10bit/24bit x PCLK.
    Please correct me, if I'm wrong.

    Thanks,
    Ken
  • 0 in reply to Kenichiro
    TI__Genius 14015 points

    Hi Ken,

    Yes, you are correct. The CSI-2 clock and data rate are based on the PCLK frequency and the lane configuration. It doesn't matter if 24 bits or 10 bits (or 12, etc.) are being output.

    Thanks,
    Jason