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TLK10031: How to know if the chip is initialized/configured correctly

Part Number: TLK10031
Other Parts Discussed in Thread: TLK10002, TLK10232, TLK10034

Hi,

After power up how do i knew if the chip is working in correct status? Currently the chip does not respond to far end 10Gb Ethernet card. I need to figure out if the TLK10031 is working properly. Asking for help.

Is there any instruction of how to initialize the TLK10031?

Very appreciate! 

  • Following is my initialization steps
    // 1. Reset device (write assert RESET_N pin longer than 1us)
    // 2. Disable auto-negotiation by writing 1’b0 to 0x07.0000 bit 12
    // 3. 0x1e.0001 = 0x0302
    // 4. 0x1e.0002 = 0x831c
    // 5. 0x01.0096 = 0x0000 ; Disable link training by writing 16’h0000 to 0x01.0096
    // 6. 0x1e.8020 = 0x03FF; This allows the link settings that would normally be configured through KR training to be configured manually instead.
    // 7. 0x1e.0004 = 0xd500.
    // 8. 0x1E.000E = ox0008 ; Issue a data path reset by writing 1’b1 to bit 3.
  • Hi Yaoting,

    For XAUI-to-SFI/XFI operation, you will need to configure the device for 10GBASE-KR mode and disable the features specific to backplane Ethernet like Clause 73 auto-negotiation and 10G link training. To do this, follow this procedure:

    1. Reset device (write a 1 to 0x1E.0000 bit 15 or assert RESET_N pin)
    2. Make sure the reference clock selection (156.25 MHz or 312.5 MHz) is correct – this is done through register 0x1E.001D bit 12 (default is 156.25 MHz).
    3. Disable auto-negotiation by writing 1’b0 to 0x07.0000 bit 12
    4. Disable link training by writing 16’h0000 to 0x01.0096
    5. Write 16’h03FF to 0x1E.8020. This allows the link settings that would normally be configured through KR training to be configured manually instead.
    6. Depending on the link conditions, you may need to change the default configuration of 0x1E.0003 and 0x1E.0004. For optical connections, we typically recommend changing HS_ENTRACK (0x1E.0004 bit 15) to 1’b1 and HS_EQPRE (0x1E.0004 bits 14:12) to 3’b101. This can be a starting point, but you may need to do some BER testing to optimize the values.
    7. Issue a data path reset by writing 1’b1 to 0x1E.000E bit 3.

    At this point the device should be properly configured. Please follow the procedure above, is needed to force the device into 10GBASE-KR mode, on the other hand, you will need to adjust the SERDES settings (HS_SERDES_CONTROL_2& 3 since the device is interfacing with optical modules).

    Best Regards,
    Luis Omar Moran
    High Speed Interface
    SWAT Team
  • Hi Luis,

    It looks like i just did what your procedure asks. Could you help me to look into my initialization steps?

    Following is my initialization steps
    // 1. Reset device (write assert RESET_N pin longer than 1us)
    // 2. 0x07.0000 = 0x1000; Disable auto-negotiation 
    // 3. 0x1e.0001 = 0x0302
    // 4. 0x1e.0002 = 0x831c
    // 5. 0x01.0096 = 0x0000 ; Disable link training
    // 6. 0x1e.8020 = 0x03FF; 
    // 7. 0x1e.0004 = 0xd500. 
    // 8. 0x1E.000E = ox0008 ; Issue a data path reset 

    Appreciate a lot.

    Yaoting

  • Please follow this procedure:

    // 1. Reset device (write assert RESET_N pin longer than 1us)
    // 2. 0x07.0000 = 0x2000; Disable auto-negotiation, you had 0x1000
    // 3. 0x01.0096 = 0x0000 ; Disable link training
    // 4. 0x1e.8020 = 0x03FF;
    // 5. 0x1e.0004 = 0xd500. //You should tune the parameters such as EQPRE, SWING, ENTRACK, CDRMULT for SFF (HS_SERDES_CONTROL_2 &3)
    // 6. 0x1E.000E = 0x0008 ; Issue a data path reset

    Regards,
    Luis
  • Hi Luis,
    It does not work by following your procedure. Is there any way in which i can verify the TLK10031 is working properly or not?
    Appreciate your helps.

    Yaoting
  • Hi Yaoting,

    Please let me know the value of these registers (once the device is configured with the procedure I suggested):

    CHANNEL_STATUS_1

    HS_ERROR_COUNTER

    LS_LN0_ERROR_COUNTER

    LS_LN1_ERROR_COUNTER

    LS_LN2_ERROR_COUNTER

    LS_LN3_ERROR_COUNTER

    LS_STATUS_1

    HS_STATUS_1

    PCS_STATUS_1

    AN_CONTROL

    LT_TRAIN_CONTROL

    On the other hand, you could perform a loopback in the high speed side, and enable the internal PRBS to double-check the device works.

    Regards,

    Luis

  • Thank you ,Luis.

    Here are the registers' values we got:

    CHANNEL_STATUS_1                                     0x150 (Hex)      

    HS_ERROR_COUNTER                                    0xffff (Hex)        

    LS_LN0_ERROR_COUNTER                           0xfffd (Hex)       

    LS_LN1_ERROR_COUNTER                           0xfffd (Hex)       

    LS_LN2_ERROR_COUNTER                           0xfffd (Hex)       

    LS_LN3_ERROR_COUNTER                           0xfffd (Hex)       

    LS_STATUS_1                                                    0x8002 (Hex)    

    HS_STATUS_1                                                   0x0 (Hex)           

    PCS_STATUS_1                                                 0x2 (Hex)           

    AN_CONTROL                                                   0x2000 (Hex)    

    LT_TRAIN_CONTROL                                      0x0 (Hex)

    Yaoting

  • Ok, please try this:

    // 1. Reset device (write assert RESET_N pin longer than 1us)

    // 2. 0x07.0000 = 0x2000; Disable auto-negotiation, you had 0x1000

    // 3. 0x01.0096 = 0x0000 ; Disable link training

    //  4. 0x000B = 0x3D18; Enable Internal PRBS Generator/Verifier and Deep Remote Loopback

    // 5. 0x1e.8020 = 0x03FF;

    // 6. 0x1e.0004 = 0xd500. //You should tune the parameters such as EQPRE, SWING, ENTRACK, CDRMULT for SFF (HS_SERDES_CONTROL_2 &3)

    // 7. 0x1E.000E = 0x0008 ; Issue a data path reset

    The data is accepted on the high speed side receive SERDES pins (HSRX*P/N), traverses the entire receive data path is returned through the entire transmit data path and sent out through the high speed side transmit SERDES pins (HSTX*P/N). The low speed side outputs on OUT*P/N pins are still available for monitoring and should be correctly terminated. The low speed side inputs on IN*P/N should be electrically idle (floating).

    Please try this "setup", connecting the HSTX to HSRX through optical cable.

    Thanks,

    Luis

  • LS_STATUS_1 0x8002 (Hex) --> 0x8003
    HS_STATUS_1 0x0 (Hex) --> 0x8
  • OK, I did as you suggested. what next? What should we check?
    Thanks
  • Please let me know the status of these registers:
    CHANNEL_STATUS_1 0x150 (Hex)

    HS_ERROR_COUNTER 0xffff (Hex)

    LS_LN0_ERROR_COUNTER 0xfffd (Hex)

    LS_LN1_ERROR_COUNTER 0xfffd (Hex)

    LS_LN2_ERROR_COUNTER 0xfffd (Hex)

    LS_LN3_ERROR_COUNTER 0xfffd (Hex)

    LS_STATUS_1 0x8002 (Hex)

    HS_STATUS_1 0x0 (Hex)

    PCS_STATUS_1 0x2 (Hex)

    Thanks,
    Luis
  • Hi Luis,

    After setting up the loopback, the following is the register result. They are pretty the same.

    CHANNEL_STATUS_1                                     0x140 (Hex)      

    HS_ERROR_COUNTER                                    0xffff (Hex)        

    LS_LN0_ERROR_COUNTER                           0xfffd (Hex)       

    LS_LN1_ERROR_COUNTER                           0xfffd (Hex)       

    LS_LN2_ERROR_COUNTER                           0xfffd (Hex)       

    LS_LN3_ERROR_COUNTER                           0xfffd (Hex)       

    LS_STATUS_1                                                    0x8000 (Hex)    

    looking forward to your further helps!

    Yaoting

    HS_STATUS_1                                                   0x1 (Hex)           

    PCS_STATUS_1                                                 0x2 (Hex)            

     

  • Hi Yaoting,

    Please try different combinations for:

    HS_ENTRACK
    HS_EQPRE
    HS_PEAK_DISABLE
    HS_H1CDRMODE

    Regards,

    Luis

  • Hi Luis,
    Please confirm the following settings
    HS_ENTRACK ="1"
    HS_EQPRE=???
    HS_PEAK_DISABLE="1"
    HS_H1CDRMODE="1"
    What about the rest bits settings in 1e.0004?
    BTW, what the cursor here means?

    Thanks
    Yaoting
  • Yaoting,

    Attached you will find a description of these parameters (ENTRACK, PEAK_DISABLE, CDRMODE, etc.)

    Unfortunately, when the device is interfacing with optical modules the link training is disabled, that sweeps all these parameters automatically to get the best combination of values to decrease the BER,  hence, the user needs to perform this procedure manually according to their system.

    Please take a look into this document to get an explanation of several parameters for the equalization of the device.

    As a start point we recommend focus in:

    HS_ENTRACK

    HS_EQPRE

    HS_PEAK_DISABLE

    HS_H1CDRMODE

    TLK10xxx SerDes Overview.ppt

    Best Regards,

    Luis

  • Luis,
    the length of differential trace on PCB (FR4) from TLK10031 HS output to Optic Fiber XCVR input is bout 7mm. In our another system we use your TLK10002 chip. It works well based on same PCB design. Do you think it still could be an analog issue in waveform?
    Could you give me some suggestion on those bits setting in 1e.0004 based on our PCB situation?
    Thanks a lot.

    Yaoting
  • Yaoting,

    Have you tried different settings for your system? It is hard to suggest a combination of values for every system since the Link Training is not available for 10GBASE-R, hence, the user should sweep different values for those registers.

    Thanks,
    Luis
  • I tried a change once. It is the same. Is there any way i can know if it works or not?
    Thanks
  • Hi Yaoting,

    Did you perform a test with different values? Unfortunately the equalization is manual and the user should try different combinations, I knos this procedure is exhaustive but with link trainning disabled this is the unique solution.

    Thanks,

    Luis

  • Hi Luis,

    I will try after i figure out what those setting really mean so as to make reasonable combinations.

    To my understanding you asked me to do that because you think the line eye diagram might be an issue, But, as i mentioned before, We have  another system in which we use your TLK10002 chip. Its pcb layout design is the same as now we did for TLK10031 at HS end. We never came up the issue of tuning the waveform but the default values before. It works well. They both work at 10Gb/s. Do you think it IS the problem for this new TLK10031 failure? Looking forward to your helps to clarify my confusing. 

    Anyway, i will follow your advice. Thanks

    Yaoting

  • Hi, Luis,
    I like you to confirm the following settings,
    HS_ENTRACK=1
    HS_PEAK_DISABLE=0 ("1" is for less than 6Gb/s)
    HS_H1CDRMODE =1 ( does 7mm long trace meet short channal?)
    the above three look like they are no other choice. Am i right?
    What i only need to change is HS_EQPRE which changes waveform amplitude, right?

    I am gonna ask you to check my schematic design. I don't know how to give you the pdf file. Can you help me?
    Thanks

    Yaoting
  • Hi Luis,
    In table 7-13 on page 57 of the data sheet, for bit[1] setting, it says,
    "HS Reference clock selection.
    1 = Selects REFCLK_0_P/N as clock reference to HS side serdes macro(Default 1’b0)
    0 = Selects REFCLK_1_P/N as clock reference to HS side serdes macro"
    Which is the power up setting, selects REFCLK_1_P/N or selects REFCLK_0_P/N ?

    Thanks

    Yaoting
  • Hi Yaoting,

    Yes, you are right, plase try with these settings as starting point. For the EQPRE:
    The setting 000 (1/9 cursor amplitude) corresponds to the greatest amount of equalization, and should be used for long (high-loss) channels.
    The setting 110 (13/9 cursor amplitude) corresponds to the least amount of equalization, and should be used for short (low-loss) channels.
    HS_SWING controls the amplitud for the transmitter.

    It seems the TLK10031 datasheet has a typo, the correct values are as follows:
    Channel HS Reference clock selection. Applicable only when REFCLK_SEL pin is LOW.
    0 = Selects REFCLK_0_P/N as clock reference to Channel x HS side serdes macro(Default 1’b0)
    1 = Selects REFCLK_1_P/N as clock reference to Channel x HS side serdes macro

    Thanks,
    Luis
  • You can send me the schematics through e-mail.

    omar.moran@ti.com

    Regards,
    Luis
  • What is register=0x1e.8020? There is no description in data sheet.
  • Register 0x1E.8020. This register allows some settings of link training can be set manually.
    VS_SERDES_CFG_OVERRIDE_CTRL Default: 0x0200
    0x1E.8020.15 LS_PLL_MULT_OVERRIDE Override PLL_MULT value going into Malfoy with MDIO configured value (Default 1’b0)
    0x1E.8020.14 LS_RATE_OVERRIDE Override RATE value going into Malfoy with MDIO configured value (Default 1’b0)
    0x1E.8020.13 HS_PLL_MULT_OVERRIDE Override PLL_MULT value going into Copperfield with MDIO configured value (Default 1’b0)
    0x1E.8020.12 HS_RATE_OVERRIDE Override RATE value going into Copperfield with MDIO configured value (Default 1’b0)
    0x1E.8020.10 HS_BUSWIDTH_OVERRIDE Override BUSWIDTH value going into Copperfield with MDIO configured value (Default 1’b0)
    0x1E.8020.9 HS_FIRUPT_OVERRIDE Override FIRUPT value going into Copperfield with MDIO configured value (Default 1’b1)
    0x1E.8020.8 HS_ENRX_OVERRIDE Override ENRX value going into Copperfield with MDIO configured value (Default 1’b0)
    0x1E.8020.7 HS_AZCAL_OVERRIDE Override AZCAL value going into Copperfield with MDIO configured value (Default 1’b0)
    0x1E.8020.6 HS_ENTRACK_OVERRIDE Override ENTRACK value going into Copperfield with MDIO configured value (Default 1’b0)
    0x1E.8020.5 HS_EQHLD_OVERRIDE Override EQHLD value going into Copperfield with MDIO configured value (Default 1’b0)
    0x1E.8020.4 HS_TWCRF_OVERRIDE Override TWCRF value going into Copperfield with MDIO configured value (Default 1’b0)
    0x1E.8020.3 HS_TWPOST2_OVERRIDE Override TWPOST2 value going into Copperfield with MDIO configured value (Default 1’b0)
    0x1E.8020.2 HS_TWPOST_OVERRIDE Override TWPOST value going into Copperfield with MDIO configured value (Default 1’b0)
    0x1E.8020.1 HS_TWPRE_OVERRIDE Override TWPRE value going into Copperfield with MDIO configured value (Default 1’b0)
    0x1E.8020.0 HS_SWING_OVERRIDE Override SWING value going into Copperfield with MDIO configured value (Default 1’b0)

    Regards
  • Is it a R/W register? I write a "3ff" to it but read back with the value of all "0".
    Is its setting critical? Could it be the problem?
  • TI KeyTo write in Reserved Registers user needs to copy the key file into the local TLK folder.

  • What is that? how to do it?
  • Hi Luis,
    I am still stuck there.
    In your datasheet, on page 32, it says, "Reference code from Texas Instruments is available for the LAM and LAS modules for easy integration
    into FPGAs." Where can i get these codes?
    I am thinking to let the chip work in 10G mode to verify if the chip is good or not.
    Thanks

    Yaoting
  • Please let me request this code. Meanwhile attached you will find a document with the LAM/LAS behavior (foil 22) for TLK10002 which is a pretty similar device.

    TLK10002 Overview and Debug Procedure (rev 3) (10).ppt

    Thanks,

    Luis

  • Hi Yaoting,

    I’ve attached the reference design package for the TLK10232 which is the dual channel version of the TLK10031.  It looks like an executable after you unzip it, but this is just so you have to agree to terms and conditions.  If you run the file, it will then install the reference code and documentation on your computer.

    TI_LANE_ALIGN_REF_DESIGN_V04.zip

    Regards,

    Luis

  • Thanks Luis.
    I found there are several loopback description, Shallow loopback, Deep loopback, PMA loopback and PCS loopback. But i don't find detail description about them in data sheet. Could you give me a more instruction about them?
  • Hello Yaoting,

    Please take a look into the TLK10034 datasheet. There is a detailed description of every kind of loopback.

    Thanks,
    Luis
  • Hi Luis,

    It looks like there is no Local Deep Loopback in TLK10031, is it ture? If i gonna do the Local deep loopback is there any other approach in stead?

    Thanks

    Yaoting

  • Hi Yaoting,

    TLK10031 is a single-channel version of TLK10232 – it was just a package spin so the registers should be the same. Please take a look into the register map of the TLK10232. Through the register 0x1E.000B bit[1] the deep local loopback is enabled.

    TLK10232_REGMAP_v8.pdf

    Regards,

    Luis