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DS92LV2421: DS92LV2421, DS92LV3222

Part Number: DS92LV2421
Other Parts Discussed in Thread: DS92LV2422, , DS92LV3221, DS92LV3222

Hi,

I have two questions regarding Channel Link II SER/DES. Please see the below my questions.

1) DS92LV2421/2422:  As you know, DS92LV2421 Serializer  has C|x pins. DS92LV2422 Deserializer has COx pins. These pins are used for  HSYNC/VSYNC/DE signals.

If LV2422 will lose the embedded clock, LOCK signal is disabled, and DO[23:0] becomes tri-stated. Display's data is asynchronized. Correct picture is not displayed on screen. But LV2422 will complete resynchronization again, Display's data  is synchronized, and correct picture is displayed on screen. Is my understanding right?

2) DS92LV3221/3222: As you know DS92LV3221/3222 does not have special pins like CIx/COx pins. So If LV3222 will lose the embedded clock, LOCK signal is disabled and RxOUT[31:0] becomes tri-stated.

Display's data is asynchronized. Correct picture is not displayed on screen. and LV3222 will complete resynchronization again, Display's data is still ashynchronized. Wrong data is on screen. So if user uses

DS92LV3221/3222 SERDES, HSYNC and VSYNC data must be sent with serialized data, and pixel data must be synchronized by external logic in receiver side. Is my understanding right?

I appreciate your quick reply.

Best regards,

Michi

  • Hi Michi,

    1) Yes, if the DS92LV2422 loses the embedded clock, LOCK is disabled, and based on the selection of OSS_SEL, the outputs will either be placed in High-Z or L (please see Table 7 of the datasheet).

    2) Once again your understanding is correct. The DS92LV3221/DS92LV3222 can transfer 32 bits of data across the 2 LVDS serial channels, but there are not additional bits available for hysnc and vsync like the DS92LV2421/DS92LV2422.

    Regards,
    Ryan